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Message-ID: <20230221015056.GA791166-robh@kernel.org>
Date:   Mon, 20 Feb 2023 19:50:56 -0600
From:   Rob Herring <robh@...nel.org>
To:     Konrad Dybcio <konrad.dybcio@...aro.org>
Cc:     linux-arm-msm@...r.kernel.org, andersson@...nel.org,
        agross@...nel.org, marijn.suijten@...ainline.org,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Stephen Boyd <sboyd@...nel.org>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Luca Weiss <luca@...tu.xyz>,
        Lorenzo Pieralisi <lpieralisi@...nel.org>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8550: Use correct CPU compatibles

On Thu, Feb 16, 2023 at 12:08:03PM +0100, Konrad Dybcio wrote:
> Use the correct compatibles for the four kinds of CPU cores used on
> SM8550, based on the value of their MIDR_EL1 registers:
> 
> CPU7: 0x411fd4e0 - CX3 r1p1
> CPU5-6: 0x412fd470 - CA710 r?p?
> CPU3-4: 0x411fd4d0 - CA715 r?p?
> CPU0-2: 0x411fd461 - CA510 r?p?
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index ff4d342c0725..a65c3151baf3 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -66,7 +66,7 @@ cpus {
>  
>  		CPU0: cpu@0 {
>  			device_type = "cpu";
> -			compatible = "qcom,kryo";
> +			compatible = "arm,cortex-a510";

Good. We should kill off the meaningless 'qcom,kryo'.

Acked-by: Rob Herring <robh@...nel.org>

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