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Message-ID: <430318ed-5b30-e549-a5ce-df83aa18adf9@linaro.org>
Date: Tue, 21 Feb 2023 12:25:41 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Xingyu Wu <xingyu.wu@...rfivetech.com>,
linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Emil Renner Berthing <kernel@...il.dk>
Cc: Rob Herring <robh+dt@...nel.org>, Conor Dooley <conor@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Hal Feng <hal.feng@...rfivetech.com>,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 01/11] dt-bindings: clock: Add StarFive JH7110
System-Top-Group clock and reset generator
On 21/02/2023 09:33, Xingyu Wu wrote:
> Add bindings for the System-Top-Group clock and reset generator (STGCRG)
> on the JH7110 RISC-V SoC by StarFive Ltd.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@...rfivetech.com>
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 93eb504c3b21..2e70c9f21989 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -19914,6 +19914,7 @@ F: arch/riscv/boot/dts/starfive/
> STARFIVE JH71X0 CLOCK DRIVERS
> M: Emil Renner Berthing <kernel@...il.dk>
> M: Hal Feng <hal.feng@...rfivetech.com>
> +M: Xingyu Wu <xingyu.wu@...rfivetech.com>
No improvements here. You add here new bindings for one device and then
- without explanation - add yourself to all Starfive clock bindings.
Either explain it or drop it or move it to separate patch.
You already got comment for this.
Best regards,
Krzysztof
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