linux-kernel - Re: [PATCH v2 02/29] LoongArch: KVM: Implement kvm module related interface

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Message-ID: <2666bd9a-1891-00b5-b195-6b35fc275ee5@xen0n.name>
Date:   Tue, 21 Feb 2023 20:38:39 +0800
From:   WANG Xuerui <kernel@...0n.name>
To:     maobibo <maobibo@...ngson.cn>, Paolo Bonzini <pbonzini@...hat.com>,
        Tianrui Zhao <zhaotianrui@...ngson.cn>
Cc:     Huacai Chen <chenhuacai@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        loongarch@...ts.linux.dev, linux-kernel@...r.kernel.org,
        kvm@...r.kernel.org, Jens Axboe <axboe@...nel.dk>,
        Mark Brown <broonie@...nel.org>,
        Alex Deucher <alexander.deucher@....com>,
        Oliver Upton <oliver.upton@...ux.dev>
Subject: Re: [PATCH v2 02/29] LoongArch: KVM: Implement kvm module related
 interface

On 2023/2/21 19:39, maobibo wrote:
> 
> 
> 在 2023/2/21 18:37, WANG Xuerui 写道:
>> On 2023/2/21 18:18, maobibo wrote:
>>>
>>>
>>> 在 2023/2/21 16:14, Paolo Bonzini 写道:
>>>> On 2/21/23 07:59, maobibo wrote:
>>>>>> Also, why does the world switch code need a copy?
>>>>> There will be problem in world switch code if there is page fault reenter,
>>>>> since pgd register is shared between root kernel and kvm hypervisor.
>>>>> World switch entry need be unmapped area, cannot be tlb mapped area.
>>>>
>>>> So if I understand correctly the processor is in direct address translation mode until the "csrwr t0, LOONGARCH_CSR_CRMD" instruction. Where does it leave paged mode?
>>> The processor still in paged mode during world switch context. For example
>>> when vm exits from guest mode to root mode, it executes world switch code
>>> from kvm_vector_entry, PC register points to HVA address, however vmid from
>>> LOONGARCH_CSR_GTLBC is not clear to root mode. If there is page fault
>>> exception, hardware treats it exception from GPA-->HPA rather than that
>>> from HVA --> HPA, since vmid info in CSR_GTLBC is not zero.
>>>
>>> In page mode, there are two kinds of address: unmapped address and
>>> tlb mapped address. For unmapped address there is only cachable/uncachable
>>> attribution, but not RWX attr; and there is no tlb handling for it.
>>> For simplicity,  unmapped address can be treated as window filtered address.
>>>
>>> It will be fully root mode only after this piece of code is executed
>>> during world switch context; vmid is zero and PC points to HVA.
>>>           ori     t0, zero, CSR_GSTAT_PVM
>>>           csrxchg zero, t0, LOONGARCH_CSR_GSTAT
>>>           /* Clear GTLBC.TGID field */
>>>           csrrd   t0, LOONGARCH_CSR_GTLBC
>>>           bstrins.w       t0, zero, CSR_GTLBC_TGID_SHIFT_END, CSR_GTLBC_TGID_SHIFT
>>>           csrwr   t0, LOONGARCH_CSR_GTLBC
>>
>> AFAIK all of these is probably coming from Volume 3 of LoongArch ISA Manual, which is unfortunately not publicly available at the moment. For sake of meaningful reviews, when can we expect to get our hands on the manuals?
> We are pushing to public the virtualization manual inside, it is convenient
> to sw developer to review the code. However I am not sure about the date :(

Well, that's kinda expected, but it's nice to see some progress and 
certainly your open attitude to this matter is constructive. Thanks for 
sharing this and looking forward to the eventual docs release then!

-- 
WANG "xen0n" Xuerui

Linux/LoongArch mailing list: https://lore.kernel.org/loongarch/