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Message-ID: <Y/T7EYISh0Zx9xWY@spud>
Date: Tue, 21 Feb 2023 17:10:41 +0000
From: Conor Dooley <conor@...nel.org>
To: Hal Feng <hal.feng@...rfivetech.com>
Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, Stephen Boyd <sboyd@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
Ben Dooks <ben.dooks@...ive.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Emil Renner Berthing <emil.renner.berthing@...onical.com>,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 05/19] reset: starfive: Factor out common JH71X0 reset
code
On Tue, Feb 21, 2023 at 10:46:31AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@...il.dk>
>
> The StarFive JH7100 SoC has additional reset controllers for audio and
> video, but the registers follow the same structure. On the JH7110 the
> reset registers don't get their own memory range, but instead follow the
> clock control registers. The registers still follow the same structure
> though, so let's factor out the common code to handle all these cases.
I think you split this out compared to the previous version of t he
series, and does look as described.
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
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