Message-ID: <CAHbLzkoimRevH7zMVUTmeu6SgmhjvOes7UoLmr=ceL1z4pwhRw@mail.gmail.com>
Date:   Wed, 22 Feb 2023 14:48:55 -0800
From:   Yang Shi <shy828301@...il.com>
To:     Matthew Wilcox <willy@...radead.org>
Cc:     linux-mm@...ck.org, linux-kernel@...r.kernel.org
Subject: Re: What size anonymous folios should we allocate?

On Tue, Feb 21, 2023 at 7:52 PM Matthew Wilcox <willy@...radead.org> wrote:
>
> On Tue, Feb 21, 2023 at 03:05:33PM -0800, Yang Shi wrote:
> > On Tue, Feb 21, 2023 at 1:49 PM Matthew Wilcox <willy@...radead.org> wrote:
> > >
> > > In a sense this question is premature, because we don't have any code
> > > in place to handle folios which are any size but PMD_SIZE or PAGE_SIZE,
> > > but let's pretend that code already exists and is just waiting for us
> > > to answer this policy question.
> > >
> > > I'd like to reject three ideas up front: 1. a CONFIG option, 2. a boot
> > > option and 3. a sysfs tunable.  It is foolish to expect the distro
> > > packager or the sysadmin to be able to make such a decision.  The
> > > correct decision will depend upon the instantaneous workload of the
> > > entire machine and we'll want different answers for different VMAs.
> >
> > Yeah, I agree those 3 options should be avoided. For some
> > architectures, there are a or multiple sweet size(s) benefiting from
> > hardware. For example, ARM64 contiguous PTE supports up to 16
> > consecutive 4K pages to form a 64K entry in TLB instead of 16 4K
> > entries. Some implementations may support intermediate sizes (for
> > example, 8K, 16K and 32K, but this may make the hardware design
> > harder), but some may not. AMD's coalesce PTE supports a different
> > size (128K if I remember correctly). So the multiple of the size
> > supported by hardware (64K or 128K) seems like the common ground from
> > maximizing hardware benefit point of view. Of course, nothing prevents
> > the kernel from allocating other orders.
>
> All of this is true (although I think AMDs intermediate size is actually
> 32kB, not 128kB), but irrelevant.  Software overhead is FAR more important
> than hardware overhead.  If we swap out the wrong page or have to run
> around doing reclaim, that absolutely dwarfs the performance impact of
> using small TLB entries.
>
> So we need to strike the right balance between using larger folios
> for efficiency and smaller folios for precision of knowing which
> pages are still part of the process working set.

As long as the large folio is not PMD mapped, we know which subpages
are accessed. Anyway I do agree we need the balance.

>
> > Actually I was thinking about the reverse, starting from the biggest
> > possible order, for example, 2M -> 1M -> ... 64K -> ... 4K. And the
> > page fault path should be able to use the same fallback order. But
> > excessive fallback tries may be harmful either.
>
> What's your reasoning here?

There is no indicator to tell kernel what order is preferred or proper
for anonymous page, just like you elaborated. We don't know the access
pattern of the workloads either. But we have to start from an order.
Basically I looked at it from the other angle. The approach just
simply starts from an order which could maximize the hardware benefit.
This may incur some memory waste until memory reclamation is kicked
in. And there should be some feedback mechanism to give a hint for a
more proper order for the future page fault off the top of my head,
then we finally reach the balance.

I can't tell which one (starting from low order or high order) is
better for now.

>
> > > B. A further modification is that it will require three of the four
> > >    folios being combined to be on the active list.  If two (or more)
> > >    of the four folios are inactive, we should leave them alone; either
> > >    they will remain inactive and eventually be evicted, or they will be
> > >    activated and eligible for merging in a future pass of khugepaged.
> >
> > If we use the fallback policy, we should be able to just leave it to
> > reclamation time. When checking reference we could tell what PTEs are
> > accessed, then split if there is significant internal fragmentation.
>
> I think it's going to lead to excessive memory usage.  There was data
> presented last LSFMM that we already have far too much memory tied up
> in THP for many workloads.

It is possible. But that data was based on PMD size THP IIRC. The
lower order may make difference hopefully.

>
> > > C. We add a new wrinkle to the LRU handling code.  When our scan of the
> > >    active list examines a folio, we look to see how many of the PTEs
> > >    mapping the folio have been accessed.  If it is fewer than half, and
> > >    those half are all in either the first or last half of the folio, we
> > >    split it.  The active half stays on the active list and the inactive
> > >    half is moved to the inactive list.
> >
> > With contiguous PTE, every PTE still maintains its own access bit (but
> > it is implementation defined, some implementations may just set access
> > bit once for one PTE in the contiguous region per arm arm IIUC). But
> > anyway this is definitely feasible.
>
> If a CPU doesn't have separate access bits for PTEs, then we should just
> not use the contiguous bits.  Knowing which parts of the folio are
> unused is more important than using the larger TLB entries.

Yeah, we are on the same page.

>
> > > For the third case, in contrast, the parent had already established
> > > an appropriate size folio to use for this VMA before calling fork().
> > > Whether it is the parent or the child causing the COW, it should probably
> > > inherit that choice and we should default to the same size folio that
> > > was already found.
> >
> > Actually this is not what THP does now. The current THP behavior is to
> > split the PMD then fallback to order-0 page fault. For smaller orders,
> > we may consider allocating a large folio.
>
> I know it's not what THP does now.  I think that's because the gap
> between PMD and PAGE size is too large and we end up wasting too much
> memory.  We also have very crude mechanisms for determining when to
> use THPs.  With the adaptive mechanism I described above, I think it's
> time to change that.

Yeah, IIRC the major reason was the complain about long latency for
COW fault. Both THP allocation and data copy could incur the long
latency. So lower order may make difference hopefully.

>

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