linux-kernel - Re: [PATCH v2] arch/powerpc/include/asm/barrier.h: redefine rmb and wmb to lwsync

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <c4dcf969-0836-cc78-63d9-db83b9ebfa1d@csgroup.eu>
Date:   Wed, 22 Feb 2023 09:43:19 +0000
From:   Christophe Leroy <christophe.leroy@...roup.eu>
To:     Kautuk Consul <kconsul@...ux.vnet.ibm.com>,
        Michael Ellerman <mpe@...erman.id.au>,
        Nicholas Piggin <npiggin@...il.com>,
        Rohan McLure <rmclure@...ux.ibm.com>
CC:     "linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2] arch/powerpc/include/asm/barrier.h: redefine rmb and
 wmb to lwsync



Le 22/02/2023 à 10:03, Kautuk Consul a écrit :
> A link from ibm.com states:
> "Ensures that all instructions preceding the call to __lwsync
>   complete before any subsequent store instructions can be executed
>   on the processor that executed the function. Also, it ensures that
>   all load instructions preceding the call to __lwsync complete before
>   any subsequent load instructions can be executed on the processor
>   that executed the function. This allows you to synchronize between
>   multiple processors with minimal performance impact, as __lwsync
>   does not wait for confirmation from each processor."
> 
> Thats why smp_rmb() and smp_wmb() are defined to lwsync.
> But this same understanding applies to parallel pipeline
> execution on each PowerPC processor.
> So, use the lwsync instruction for rmb() and wmb() on the PPC
> architectures that support it.
> 
> Signed-off-by: Kautuk Consul <kconsul@...ux.vnet.ibm.com>

Reviewed-by: Christophe Leroy <christophe.leroy@...roup.eu>

> ---
>   arch/powerpc/include/asm/barrier.h | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/arch/powerpc/include/asm/barrier.h b/arch/powerpc/include/asm/barrier.h
> index b95b666f0374..e088dacc0ee8 100644
> --- a/arch/powerpc/include/asm/barrier.h
> +++ b/arch/powerpc/include/asm/barrier.h
> @@ -36,8 +36,15 @@
>    * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio.
>    */
>   #define __mb()   __asm__ __volatile__ ("sync" : : : "memory")
> +
> +/* The sub-arch has lwsync. */
> +#if defined(CONFIG_PPC64) || defined(CONFIG_PPC_E500MC)
> +#define __rmb() __asm__ __volatile__ ("lwsync" : : : "memory")
> +#define __wmb() __asm__ __volatile__ ("lwsync" : : : "memory")

I'd have preferred with 'asm volatile' though.

> +#else
>   #define __rmb()  __asm__ __volatile__ ("sync" : : : "memory")
>   #define __wmb()  __asm__ __volatile__ ("sync" : : : "memory")
> +#endif
>   
>   /* The sub-arch has lwsync */
>   #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_E500MC)