linux-kernel - Re: [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC

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Message-Id: <167707802193.24438.5407460288169239541.git-patchwork-notify@kernel.org>
Date:   Wed, 22 Feb 2023 15:00:21 +0000
From:   patchwork-bot+linux-riscv@...nel.org
To:     Hal Feng <hal.feng@...rfivetech.com>
Cc:     linux-riscv@...ts.infradead.org, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, sboyd@...nel.org,
        mturquette@...libre.com, p.zabel@...gutronix.de,
        robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        conor@...nel.org, palmer@...belt.com, paul.walmsley@...ive.com,
        aou@...s.berkeley.edu, ben.dooks@...ive.com,
        daniel.lezcano@...aro.org, tglx@...utronix.de, maz@...nel.org,
        emil.renner.berthing@...onical.com, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 00/19] Basic clock,
 reset & device tree support for StarFive JH7110 RISC-V SoC

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@...osinc.com>:

On Tue, 21 Feb 2023 10:46:26 +0800 you wrote:
> This patch series adds basic clock, reset & DT support for StarFive
> JH7110 SoC. Patch 17 depends on series [1] which provides pinctrl
> dt-bindings. Patch 19 depends on series [2] which provides dt-bindings
> of VisionFive 2 board and JH7110 SoC.
> 
> You can simply review or test the patches at the link [3].
> 
> [...]

Here is the summary with links:
  - [v4,01/19] clk: starfive: Factor out common JH7100 and JH7110 code
    (no matching commit)
  - [v4,02/19] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h
    https://git.kernel.org/riscv/c/f3af3b0039fe
  - [v4,03/19] clk: starfive: Rename "jh7100" to "jh71x0" for the common code
    (no matching commit)
  - [v4,04/19] reset: Create subdirectory for StarFive drivers
    (no matching commit)
  - [v4,05/19] reset: starfive: Factor out common JH71X0 reset code
    (no matching commit)
  - [v4,06/19] reset: starfive: Extract the common JH71X0 reset code
    (no matching commit)
  - [v4,07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code
    (no matching commit)
  - [v4,08/19] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
    (no matching commit)
  - [v4,09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
    (no matching commit)
  - [v4,10/19] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
    (no matching commit)
  - [v4,11/19] clk: starfive: Add StarFive JH7110 system clock driver
    (no matching commit)
  - [v4,12/19] clk: starfive: Add StarFive JH7110 always-on clock driver
    (no matching commit)
  - [v4,13/19] reset: starfive: Add StarFive JH7110 reset driver
    (no matching commit)
  - [v4,14/19] dt-bindings: timer: Add StarFive JH7110 clint
    (no matching commit)
  - [v4,15/19] dt-bindings: interrupt-controller: Add StarFive JH7110 plic
    (no matching commit)
  - [v4,16/19] dt-bindings: riscv: Add SiFive S7 compatible
    (no matching commit)
  - [v4,17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree
    (no matching commit)
  - [v4,18/19] riscv: dts: starfive: Add StarFive JH7110 pin function definitions
    (no matching commit)
  - [v4,19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
    (no matching commit)

You are awesome, thank you!
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