| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <56ed6a30-9815-002f-8174-95e7e9fc0954@linaro.org>
Date: Wed, 22 Feb 2023 18:08:25 +0100
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Bryan O'Donoghue <bryan.odonoghue@...aro.org>, agross@...nel.org,
andersson@...nel.org, djakov@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org
Cc: linux-arm-msm@...r.kernel.org, linux-pm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
benl@...areup.com, shawn.guo@...aro.org, fabien.parent@...aro.org,
leo.yan@...aro.org, dmitry.baryshkov@...aro.org,
stephan@...hold.net, Jun Nie <jun.nie@...aro.org>,
James Willcox <jwillcox@...areup.com>,
Joseph Gates <jgates@...areup.com>,
Max Chen <mchen@...areup.com>, Zac Crosby <zac@...areup.com>,
Vincent Knecht <vincent.knecht@...loo.org>
Subject: Re: [PATCH v6 2/5] arm64: dts: qcom: Add msm8939 SoC
On 22.02.2023 13:04, Bryan O'Donoghue wrote:
> Add msm8939 a derivative SoC of msm8916. This SoC contains a number of key
> differences to msm8916.
>
> - big.LITTLE Octa Core - quad 1.5GHz + quad 1.0GHz
> - DRAM 1x800 LPDDR3
> - Camera 4+4 lane CSI
> - Venus @ 1080p60 HEVC
> - DSI x 2
> - Adreno A405
> - WiFi wcn3660/wcn3680b 802.11ac
>
> Co-developed-by: Shawn Guo <shawn.guo@...aro.org>
> Signed-off-by: Shawn Guo <shawn.guo@...aro.org>
> Co-developed-by: Jun Nie <jun.nie@...aro.org>
> Signed-off-by: Jun Nie <jun.nie@...aro.org>
> Co-developed-by: Benjamin Li <benl@...areup.com>
> Signed-off-by: Benjamin Li <benl@...areup.com>
> Co-developed-by: James Willcox <jwillcox@...areup.com>
> Signed-off-by: James Willcox <jwillcox@...areup.com>
> Co-developed-by: Leo Yan <leo.yan@...aro.org>
> Signed-off-by: Leo Yan <leo.yan@...aro.org>
> Co-developed-by: Joseph Gates <jgates@...areup.com>
> Signed-off-by: Joseph Gates <jgates@...areup.com>
> Co-developed-by: Max Chen <mchen@...areup.com>
> Signed-off-by: Max Chen <mchen@...areup.com>
> Co-developed-by: Zac Crosby <zac@...areup.com>
> Signed-off-by: Zac Crosby <zac@...areup.com>
> Co-developed-by: Vincent Knecht <vincent.knecht@...loo.org>
> Signed-off-by: Vincent Knecht <vincent.knecht@...loo.org>
> Co-developed-by: Stephan Gerhold <stephan@...hold.net>
> Signed-off-by: Stephan Gerhold <stephan@...hold.net>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
> ---
Couple of nits below
> arch/arm64/boot/dts/qcom/msm8939.dtsi | 2454 +++++++++++++++++++++++++
> 1 file changed, 2454 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/msm8939.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi
[...]
> + mpss: remoteproc@...0000 {
> + compatible = "qcom,msm8916-mss-pil";
> + reg = <0x04080000 0x100>,
> + <0x04020000 0x040>;
I see veeery aggressive line wrapping in reg/compatible :P
> +
Unnecessary newline
> + reg-names = "qdsp6", "rmb";
> +
> + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
> + <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready",
> + "handover", "stop-ack";
This should be a vertical list
> +
> + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
> + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
> + <&gcc GCC_BOOT_ROM_AHB_CLK>,
> + <&rpmcc RPM_SMD_XO_CLK_SRC>;
> + clock-names = "iface", "bus", "mem", "xo";
This could also be one
> +
> + power-domains = <&rpmpd MSM8939_VDDMDCX>,
> + <&rpmpd MSM8939_VDDMX>;
> + power-domain-names = "cx", "mx";
> +
> + qcom,smem-states = <&hexagon_smp2p_out 0>;
> + qcom,smem-state-names = "stop";
> +
> + resets = <&scm 0>;
> + reset-names = "mss_restart";
> +
> + qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
> +
> + status = "disabled";
> +
> + mba {
> + memory-region = <&mba_mem>;
> + };
> +
> + mpss {
> + memory-region = <&mpss_mem>;
> + };
> +
> + smd-edge {
> + interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
> +
> + qcom,smd-edge = <0>;
> + mboxes = <&apcs1_mbox 12>;
> + qcom,remote-pid = <1>;
> +
> + label = "hexagon";
> + };
> + };
> +
[...]
> +
> + blsp1_uart1: serial@...f000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0x078af000 0x200>;
> + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + dmas = <&blsp_dma 0>, <&blsp_dma 1>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&blsp1_uart1_default>;
> + pinctrl-1 = <&blsp1_uart1_sleep>;
property
property-names
> + status = "disabled";
> + };
> +
[...]
> + usb: usb@...9000 {
> + compatible = "qcom,ci-hdrc";
> + reg = <0x078d9000 0x200>,
> + <0x078d9200 0x200>;
> + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_USB_HS_AHB_CLK>,
> + <&gcc GCC_USB_HS_SYSTEM_CLK>;
> + clock-names = "iface", "core";
> + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
> + assigned-clock-rates = <80000000>;
> + resets = <&gcc GCC_USB_HS_BCR>;
> + reset-names = "core";
> + #reset-cells = <1>;
> + phy_type = "ulpi";
> + dr_mode = "otg";
> + ahb-burst-config = <0>;
> + phy-names = "usb-phy";
> + phys = <&usb_hs_phy>;
> + status = "disabled";
> +
> + ulpi {
> + usb_hs_phy: phy {
> + compatible = "qcom,usb-hs-phy-msm8916",
> + "qcom,usb-hs-phy";
> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
This could be wrapped
> + clock-names = "ref", "sleep";
> + resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
> + reset-names = "phy", "por";
> + #phy-cells = <0>;
> + qcom,init-seq = /bits/ 8 <0x0 0x44>,
> + <0x1 0x6b>,
> + <0x2 0x24>,
> + <0x3 0x13>;
> + };
> + };
> + };
[...]
> +
> + pronto: remoteproc@...4000 {
> + compatible = "qcom,pronto-v2-pil", "qcom,pronto";
> + reg = <0x0a204000 0x2000>,
> + <0x0a202000 0x1000>,
> + <0x0a21b000 0x3000>;
> + reg-names = "ccu", "dxe", "pmu";
> +
> + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
> + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
Long enough to be a vertical list
Konrad
> +
> + memory-region = <&wcnss_mem>;
> +
> + power-domains = <&rpmpd MSM8939_VDDCX>,
> + <&rpmpd MSM8939_VDDMX>;
> + power-domain-names = "cx", "mx";
> +
> + qcom,smem-states = <&wcnss_smp2p_out 0>;
> + qcom,smem-state-names = "stop";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&wcnss_pin_a>;
> +
> + status = "disabled";
> +
> + iris {
> + compatible = "qcom,wcn3620";
> + clocks = <&rpmcc RPM_SMD_RF_CLK2>;
> + clock-names = "xo";
> + };
> +
> + smd-edge {
> + interrupts = <GIC_SPI 142 1>;
> + qcom,ipc = <&apcs1_mbox 8 17>;
> + qcom,smd-edge = <6>;
> + qcom,remote-pid = <4>;
> +
> + label = "pronto";
> +
> + wcnss {
> + compatible = "qcom,wcnss";
> + qcom,smd-channels = "WCNSS_CTRL";
> +
> + qcom,mmio = <&pronto>;
> +
> + bluetooth {
> + compatible = "qcom,wcnss-bt";
> + };
> +
> + wifi {
> + compatible = "qcom,wcnss-wlan";
> +
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "tx", "rx";
> +
> + qcom,smem-states = <&apps_smsm 10>,
> + <&apps_smsm 9>;
> + qcom,smem-state-names = "tx-enable",
> + "tx-rings-empty";
> + };
> + };
> + };
> + };
> + };
> +
> + thermal_zones: thermal-zones {
> + cpu0-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens 5>;
> +
> + trips {
> + cpu0_alert: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu0_crit: trip1 {
> + temperature = <115000>;
> + hysteresis = <0>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu0_alert>;
> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> +
> + cpu1-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens 6>;
> +
> + trips {
> + cpu1_alert: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu1_crit: trip1 {
> + temperature = <110000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu1_alert>;
> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> +
> + cpu2-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens 7>;
> +
> + trips {
> + cpu2_alert: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu2_crit: trip1 {
> + temperature = <110000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu2_alert>;
> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> +
> + cpu3-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens 8>;
> +
> + trips {
> + cpu3_alert: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu3_crit: trip1 {
> + temperature = <110000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu3_alert>;
> + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> +
> + cpu4567-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens 9>;
> +
> + trips {
> + cpu4567_alert: trip0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu4567_crit: trip1 {
> + temperature = <110000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu4567_alert>;
> + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> +
> + gpu-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens 3>;
> +
> + trips {
> + gpu_alert0: trip-point0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + gpu_crit: gpu_crit {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> + };
> +
> + modem1-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens 0>;
> +
> + trips {
> + modem1_alert0: trip-point0 {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "hot";
> + };
> + };
> + };
> +
> + modem2-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens 2>;
> +
> + trips {
> + modem2_alert0: trip-point0 {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "hot";
> + };
> + };
> + };
> +
> + camera-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsens 1>;
> +
> + trips {
> + cam_alert0: trip-point0 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "hot";
> + };
> + };
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +};
Powered by blists - more mailing lists