linux-kernel - Re: [PATCH v1 3/3] riscv: dts: starfive: jh7110: Add PLL clock node

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Message-ID: <84a785bb-8a48-fa55-ea64-29c21ac42cf8@starfivetech.com>
Date:   Thu, 23 Feb 2023 17:03:36 +0800
From:   Xingyu Wu <xingyu.wu@...rfivetech.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
CC:     <linux-riscv@...ts.infradead.org>, <devicetree@...r.kernel.org>,
        "Michael Turquette" <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Emil Renner Berthing <kernel@...il.dk>,
        Rob Herring <robh+dt@...nel.org>,
        Conor Dooley <conor@...nel.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Hal Feng <hal.feng@...rfivetech.com>,
        <linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>
Subject: Re: [PATCH v1 3/3] riscv: dts: starfive: jh7110: Add PLL clock node

On 2023/2/23 16:52, Krzysztof Kozlowski wrote:
> On 23/02/2023 09:47, Xingyu Wu wrote:
>> On 2023/2/22 17:09, Krzysztof Kozlowski wrote:
>>> On 21/02/2023 15:11, Xingyu Wu wrote:
>>>> Add the PLL clock node for the Starfive JH7110 SoC and
>>>> modify the SYSCRG node to add PLL clocks.
>>>>
>>>> Signed-off-by: Xingyu Wu <xingyu.wu@...rfivetech.com>
>>>> ---
>>>>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++--
>>>>  1 file changed, 13 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>>>> index b6612c53d0d2..0cb8d86ebce5 100644
>>>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>>>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>>>> @@ -461,12 +461,16 @@ syscrg: clock-controller@...20000 {
>>>>  				 <&gmac1_rgmii_rxin>,
>>>>  				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
>>>>  				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
>>>> -				 <&tdm_ext>, <&mclk_ext>;
>>>> +				 <&tdm_ext>, <&mclk_ext>,
>>>> +				 <&pllclk JH7110_CLK_PLL0_OUT>,
>>>> +				 <&pllclk JH7110_CLK_PLL1_OUT>,
>>>> +				 <&pllclk JH7110_CLK_PLL2_OUT>;
>>>>  			clock-names = "osc", "gmac1_rmii_refin",
>>>>  				      "gmac1_rgmii_rxin",
>>>>  				      "i2stx_bclk_ext", "i2stx_lrck_ext",
>>>>  				      "i2srx_bclk_ext", "i2srx_lrck_ext",
>>>> -				      "tdm_ext", "mclk_ext";
>>>> +				      "tdm_ext", "mclk_ext",
>>>> +				      "pll0_out", "pll1_out", "pll2_out";
>>>>  			#clock-cells = <1>;
>>>>  			#reset-cells = <1>;
>>>>  		};
>>>> @@ -476,6 +480,13 @@ sys_syscon: syscon@...30000 {
>>>>  			reg = <0x0 0x13030000 0x0 0x1000>;
>>>>  		};
>>>>  
>>>> +		pllclk: pll-clock-controller {
>>>
>>> Does not look like you tested the DTS against bindings. Please run `make
>>> dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
>>> for instructions). You should see here warnings of mixing non-MMIO nodes
>>> in MMIO-bus.
>>>
>> 
>> Oh I cherry-pick the commit of syscon node and it also include the MMC node.
>> I will remove the MMC node. 
>> I used dtbs_check and get the error 'should not be valid under {'type': 'object'}',
>> If I move this node out of the 'soc' node, the dtbs_check will be pass.
>> Is it OK to move the PLL node out of the 'soc' node? Thanks.
> 
> Shall it be out side of soc? How it can then do anything with registers?
> This does not look like correct representation of hardware.

The error appears to be due to a lack of reg base about PLL node. PLL do something with register
by 'sys_syscon' node and the syscon node is in the soc node.

Best regards,
Xingyu Wu