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Message-ID: <20230223180531.15148-4-enachman@marvell.com>
Date: Thu, 23 Feb 2023 20:05:27 +0200
From: Elad Nachman <enachman@...vell.com>
To: <thomas.petazzoni@...tlin.com>, <bhelgaas@...gle.com>,
<lpieralisi@...nel.org>, <robh@...nel.org>, <kw@...ux.com>,
<krzysztof.kozlowski+dt@...aro.org>, <linux-pci@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC: Yuval Shaia <yshaia@...vell.com>
Subject: [PATCH v3 3/7] PCI: armada8k: Add MSI support for AC5 SoC
From: Yuval Shaia <yshaia@...vell.com>
AC5 requires different handling for MSI as with armada8k.
Fix it by:
1. Enabling the relevant bits in init phase
2. Dispatch virtual IRQ handlers when MSI interrupts are received
Also enable/disable PCIE_APP_LTSSM for AC5.
Signed-off-by: Yuval Shaia <yshaia@...vell.com>
Signed-off-by: Vadym Kochan <vadym.kochan@...ision.eu>
---
v2:
1) fix W1 warnings which caused by unused leftover code
2) fix type in "requieres" word in the description
drivers/pci/controller/dwc/pcie-armada8k.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c
index b9fb1375dc58..02481ecadd25 100644
--- a/drivers/pci/controller/dwc/pcie-armada8k.c
+++ b/drivers/pci/controller/dwc/pcie-armada8k.c
@@ -50,6 +50,7 @@ struct armada8k_pcie_of_data {
#define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0)
#define PCIE_APP_LTSSM_EN BIT(2)
+#define PCIE_APP_LTSSM_EN_AC5 BIT(24)
#define PCIE_DEVICE_TYPE_SHIFT 4
#define PCIE_DEVICE_TYPE_MASK 0xF
#define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */
@@ -69,6 +70,7 @@ struct armada8k_pcie_of_data {
#define PCIE_INT_B_ASSERT_MASK_AC5 BIT(13)
#define PCIE_INT_C_ASSERT_MASK_AC5 BIT(14)
#define PCIE_INT_D_ASSERT_MASK_AC5 BIT(15)
+#define PCIE_MSI_MASK_AC5 BIT(11)
#define PCIE_ATU_ACCESS_MASK_AC5 GENMASK(21, 20)
@@ -184,6 +186,16 @@ static int armada8k_pcie_start_link(struct dw_pcie *pci)
return 0;
}
+static void ac5_pcie_msi_init(struct dw_pcie *pci)
+{
+ u32 val;
+
+ /* Set MSI bit in interrupt mask */
+ val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG);
+ val |= PCIE_MSI_MASK_AC5;
+ dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, val);
+}
+
static int armada8k_pcie_host_init(struct dw_pcie_rp *pp)
{
u32 reg;
@@ -193,7 +205,10 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp)
if (!dw_pcie_link_up(pci)) {
/* Disable LTSSM state machine to enable configuration */
reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
- reg &= ~(PCIE_APP_LTSSM_EN);
+ if (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5)
+ reg &= ~(PCIE_APP_LTSSM_EN_AC5);
+ else
+ reg &= ~(PCIE_APP_LTSSM_EN);
dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
}
@@ -233,6 +248,9 @@ static int armada8k_pcie_host_init(struct dw_pcie_rp *pp)
dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg);
}
+ if (IS_ENABLED(CONFIG_PCI_MSI) && (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5))
+ ac5_pcie_msi_init(pci);
+
return 0;
}
@@ -249,6 +267,8 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
*/
val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG);
dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val);
+ if ((PCIE_MSI_MASK_AC5 & val) && (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5))
+ dw_handle_msi_irq(&pci->pp);
return IRQ_HANDLED;
}
--
2.17.1
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