linux-kernel - Re: [PATCH net-next v6] net: phy: intel-xway: Add RGMII internal delay configuration

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Date:   Fri, 24 Feb 2023 09:04:49 +0100
From:   Michael Walle <michael@...le.cc>
To:     Martin Schiller <ms@....tdt.de>
Cc:     tharvey@...eworks.com, andrew@...n.ch, davem@...emloft.net,
        f.fainelli@...il.com, hauke@...ke-m.de, hkallweit1@...il.com,
        kuba@...nel.org, linux-kernel@...r.kernel.org,
        linux@...linux.org.uk, martin.blumenstingl@...glemail.com,
        netdev@...r.kernel.org
Subject: Re: [PATCH net-next v6] net: phy: intel-xway: Add RGMII internal
 delay configuration

Hi Martin,

Am 2023-02-24 07:25, schrieb Martin Schiller:
> On 2023-02-22 17:04, Michael Walle wrote:
>> Hi Tim, Hi Martin,
>> 
>>> I've got some boards with the GPY111 phy on them and I'm finding that
>>> modifying XWAY_MDIO_MIICTRL to change the skew has no effect unless I
>>> do a soft reset (BCMR_RESET) first. I don't see anything in the
>>> datasheet which specifies this to be the case so I'm interested it
>>> what you have found. Are you sure adjusting the skews like this
>>> without a soft (or hard pin based) reset actually works?
>> 
>> I do have the same PHY and I'm puzzled with the delay settings. Do
>> you have an EEPROM attached to the PHY? According to my datasheet,
>> that seems to make a difference. Apparently, only if there is an
>> EEPROM, you can change the value (the value is then also written to
>> the EEPROM according the datasheet).
>> If you don't have one, the values will get overwritten by the
>> external strappings on a soft reset. Therefore, it seems they cannot
>> be set. (FWIW there is also a sticky bit, but that doesn't seem to
>> help in this case).
>> 
>> -michael
> 
> Yes, you are right. The datasheet says: "In no-EEPROM mode, writing to
> this register has no impact on operation of the device".
> 
> But changing this settings without an EEPROM indeed has an impact.
> 
> We don't use an EEPROM and without tuning this values some boards are
> unable to communicate on the ethernet port(s).

Thanks for confirming! Could you share your PHYID1/PHYID2 register and
firmware version (FWV, 0x1E) contents?

In our case, any changes in MIICTRL are lost after a soft reset.

> I varied these values during operation in the uboot and was able to 
> test
> the limits very nicely.

So I guess, the value you write into MIICTRL are retained on a soft 
reset.
I.e.

mii write <phyad> 0x17 0xffff
mii write <phyad> 0x00 0x8000
mii read <phyad> 0x17

will still return 0xffff?

> 
> I wouldn't have introduced this feature if it hasn't got any impact.

Sure, I'm just trying to figure out the differences ;)

Thanks,
Michael