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Message-ID: <20230224102438.6541-9-r-gunasekaran@ti.com>
Date: Fri, 24 Feb 2023 15:54:38 +0530
From: Ravi Gunasekaran <r-gunasekaran@...com>
To: <nm@...com>, <afd@...com>, <vigneshr@...com>, <kristo@...nel.org>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<s-vadapalli@...com>, <vaishnav.a@...com>, <r-gunasekaran@...com>
CC: <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH v11 8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe
From: Aswath Govindraju <a-govindraju@...com>
x1 lane PCIe slot in the common processor board is enabled and connected to
J721S2 SOM. Add PCIe DT node in common processor board to reflect the
same.
Reviewed-by: Siddharth Vadapalli <s-vadapalli@...com>
Signed-off-by: Aswath Govindraju <a-govindraju@...com>
Signed-off-by: Vignesh Raghavendra <vigneshr@...com>
Signed-off-by: Matt Ranostay <mranostay@...com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@...com>
---
Changes from v10:
* Removed Link tag from commit message
Changes from v9:
* No change
Changes from v8:
* No change
Changes from v7:
* No change
Changes from v6:
* Removed pcie_ep node update
Changes from v5:
* No change
Changes from v4:
* No change
Changes from v3:
* No change
Changes from v2:
* Patch newly added to the series
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 76b420379645..b195f250891a 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -386,6 +386,14 @@
};
};
+&pcie1_rc {
+ status = "okay";
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
--
2.17.1
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