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Message-ID: <20230224154941.68587-4-kyarlagadda@nvidia.com>
Date: Fri, 24 Feb 2023 21:19:41 +0530
From: Krishna Yarlagadda <kyarlagadda@...dia.com>
To: <robh+dt@...nel.org>, <broonie@...nel.org>, <peterhuewe@....de>,
<jgg@...pe.ca>, <jarkko@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <linux-spi@...r.kernel.org>,
<linux-tegra@...r.kernel.org>, <linux-integrity@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
CC: <thierry.reding@...il.com>, <jonathanh@...dia.com>,
<skomatineni@...dia.com>, <ldewangan@...dia.com>,
Krishna Yarlagadda <kyarlagadda@...dia.com>
Subject: [Patch V4 3/3] spi: tegra210-quad: set half duplex flag
Tegra QSPI controller only supports half duplex transfers.
Set half duplex constrain flag.
Signed-off-by: Krishna Yarlagadda <kyarlagadda@...dia.com>
---
drivers/spi/spi-tegra210-quad.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c
index 39dec2dc161b..fe15fa6eecd1 100644
--- a/drivers/spi/spi-tegra210-quad.c
+++ b/drivers/spi/spi-tegra210-quad.c
@@ -1553,6 +1553,7 @@ static int tegra_qspi_probe(struct platform_device *pdev)
master->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_CS_HIGH |
SPI_TX_DUAL | SPI_RX_DUAL | SPI_TX_QUAD | SPI_RX_QUAD;
master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
+ master->flags = SPI_CONTROLLER_HALF_DUPLEX;
master->setup = tegra_qspi_setup;
master->transfer_one_message = tegra_qspi_transfer_one_message;
master->num_chipselect = 1;
--
2.17.1
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