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Message-Id: <20230225094246.261697-3-y.oudjana@protonmail.com>
Date: Sat, 25 Feb 2023 12:42:44 +0300
From: Yassine Oudjana <yassine.oudjana@...il.com>
To: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Daniel Golle <daniel@...rotopia.org>,
Allen-KH Cheng <allen-kh.cheng@...iatek.com>,
Tinghan Shen <tinghan.shen@...iatek.com>,
Chen-Yu Tsai <wenst@...omium.org>,
Edward-JW Yang <edward-jw.yang@...iatek.com>,
Johnson Wang <johnson.wang@...iatek.com>,
Fabien Parent <fparent@...libre.com>,
Chun-Jie Chen <chun-jie.chen@...iatek.com>,
Miles Chen <miles.chen@...iatek.com>,
Bartosz Golaszewski <bgolaszewski@...libre.com>
Cc: Yassine Oudjana <y.oudjana@...tonmail.com>,
Yassine Oudjana <yassine.oudjana@...il.com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, linux-mediatek@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, Rob Herring <robh@...nel.org>
Subject: [PATCH v3 2/4] dt-bindings: reset: Add MediaTek MT6735 reset bindings
From: Yassine Oudjana <y.oudjana@...tonmail.com>
Add reset definitions for the main reset controllers of MT6735 (infracfg
and pericfg).
Signed-off-by: Yassine Oudjana <y.oudjana@...tonmail.com>
Acked-by: Rob Herring <robh@...nel.org>
---
MAINTAINERS | 4 ++-
.../reset/mediatek,mt6735-infracfg.h | 31 +++++++++++++++++++
.../reset/mediatek,mt6735-pericfg.h | 31 +++++++++++++++++++
3 files changed, 65 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h
create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 5323f71c48fb..f617042790ee 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13101,7 +13101,7 @@ S: Maintained
F: Documentation/devicetree/bindings/mmc/mtk-sd.yaml
F: drivers/mmc/host/mtk-sd.c
-MEDIATEK MT6735 CLOCK DRIVERS
+MEDIATEK MT6735 CLOCK & RESET DRIVERS
M: Yassine Oudjana <y.oudjana@...tonmail.com>
L: linux-clk@...r.kernel.org
L: linux-mediatek@...ts.infradead.org (moderated for non-subscribers)
@@ -13110,6 +13110,8 @@ F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h
F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h
F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h
F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h
+F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h
+F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h
MEDIATEK MT76 WIRELESS LAN DRIVER
M: Felix Fietkau <nbd@....name>
diff --git a/include/dt-bindings/reset/mediatek,mt6735-infracfg.h b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h
new file mode 100644
index 000000000000..5d24c7a1317f
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RESET_MT6735_INFRACFG_H
+#define _DT_BINDINGS_RESET_MT6735_INFRACFG_H
+
+#define RST_EMI_REG 0
+#define RST_DRAMC0_AO 1
+#define RST_AP_CIRQ_EINT 3
+#define RST_APXGPT 4
+#define RST_SCPSYS 5
+#define RST_KP 6
+#define RST_PMIC_WRAP 7
+#define RST_CLDMA_AO_TOP 8
+#define RST_EMI 16
+#define RST_CCIF 17
+#define RST_DRAMC0 18
+#define RST_EMI_AO_REG 19
+#define RST_CCIF_AO 20
+#define RST_TRNG 21
+#define RST_SYS_CIRQ 22
+#define RST_GCE 23
+#define RST_M4U 24
+#define RST_CCIF1 25
+#define RST_CLDMA_TOP_PD 26
+#define RST_CBIP_P2P_MFG 27
+#define RST_CBIP_P2P_APMIXED 28
+#define RST_CBIP_P2P_CKSYS 29
+#define RST_CBIP_P2P_MIPI 30
+#define RST_CBIP_P2P_DDRPHY 31
+
+#endif
diff --git a/include/dt-bindings/reset/mediatek,mt6735-pericfg.h b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
new file mode 100644
index 000000000000..90ee8ed8923f
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_RESET_MT6735_PERICFG_H
+#define _DT_BINDINGS_RESET_MT6735_PERICFG_H
+
+#define RST_UART0 0
+#define RST_UART1 1
+#define RST_UART2 2
+#define RST_UART3 3
+#define RST_UART4 4
+#define RST_BTIF 6
+#define RST_DISP_PWM_PERI 7
+#define RST_PWM 8
+#define RST_AUXADC 10
+#define RST_DMA 11
+#define RST_IRDA 12
+#define RST_IRTX 13
+#define RST_THERM 16
+#define RST_MSDC2 17
+#define RST_MSDC3 17
+#define RST_MSDC0 19
+#define RST_MSDC1 20
+#define RST_I2C0 22
+#define RST_I2C1 23
+#define RST_I2C2 24
+#define RST_I2C3 25
+#define RST_USB 28
+
+#define RST_SPI0 33
+
+#endif
--
2.39.2
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