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Message-ID: <6aaebbc4-9d60-6445-7066-a9a60c50c6dd@starfivetech.com>
Date: Tue, 28 Feb 2023 16:55:06 +0800
From: Changhuang Liang <changhuang.liang@...rfivetech.com>
To: Rob Herring <robh@...nel.org>
CC: Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Emil Renner Berthing <kernel@...il.dk>,
Conor Dooley <conor@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Philipp Zabel <p.zabel@...gutronix.de>,
Jack Zhu <jack.zhu@...rfivetech.com>,
<linux-phy@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>
Subject: Re: [PATCH v2 1/3] dt-bindings: phy: Add starfive,jh7110-dphy-rx
On 2023/2/28 2:34, Rob Herring wrote:
> On Wed, Feb 22, 2023 at 05:59:50PM -0800, Changhuang Liang wrote:
[...]
>> +
>> + clocks:
>> + maxItems: 3
>> +
>> + clock-names:
>> + items:
>> + - const: cfg
>> + - const: ref
>> + - const: tx
>
> Should be 'rx' given this is the 'rx' block? A description of each clock
> in 'clocks' would be good.
>
'tx': This clock is directly used to generate transmit escape sequences,
will add description of each clock in 'clocks'.
>> +
>> + resets:
>> + items:
>> + - description: DPHY_HW reset
>> + - description: DPHY_B09_ALWAYS_ON reset
>> +
>> + starfive,aon-syscon:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + items:
>> + items:
>
> - items: ?
>
> Otherwise, multiple 2 cell entries are allowed. Is that intended?
>
Will change to:
items:
- items:
>> + - description: phandle of AON SYSCON
>> + - description: register offset
>> + description: The power of dphy rx is configured by AON SYSCON
>> + in this property.
>
>
>> +
>> + "#phy-cells":
>> + const: 0
>> +
>> +required:
>> + - compatible
>> + - reg
[...]
>> --
>> 2.25.1
>>
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