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Message-Id: <20230228104741.717819-17-angelogioacchino.delregno@collabora.com>
Date: Tue, 28 Feb 2023 11:47:39 +0100
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: matthias.bgg@...il.com
Cc: robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
angelogioacchino.delregno@...labora.com,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, wenst@...omium.org
Subject: [PATCH v3 16/18] arm64: dts: mediatek: mt8186: Add GPU node
Add a GPU node for MT8186 SoC but keep it disabled.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Reviewed-by: Chen-Yu Tsai <wenst@...omium.org>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index a0d3e1f731bd..78ff8ba5718e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1075,6 +1075,23 @@ mfgsys: clock-controller@...00000 {
#clock-cells = <1>;
};
+ gpu: gpu@...40000 {
+ compatible = "mediatek,mt8186-mali",
+ "arm,mali-bifrost";
+ reg = <0 0x13040000 0 0x4000>;
+
+ clocks = <&mfgsys CLK_MFG_BG3D>;
+ interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "job", "mmu", "gpu";
+ power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>,
+ <&spm MT8186_POWER_DOMAIN_MFG3>;
+ power-domain-names = "core0", "core1";
+ #cooling-cells = <2>;
+ status = "disabled";
+ };
+
mmsys: syscon@...00000 {
compatible = "mediatek,mt8186-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
--
2.39.2
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