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Message-ID: <f4dcb4f8-c70b-3ca9-33fd-8889899d7481@arm.com>
Date: Tue, 28 Feb 2023 11:35:49 +0000
From: Suzuki K Poulose <suzuki.poulose@....com>
To: Tao Zhang <quic_taozha@...cinc.com>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Konrad Dybcio <konradybcio@...il.com>,
Mike Leach <mike.leach@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc: Jinlong Mao <quic_jinlmao@...cinc.com>,
Leo Yan <leo.yan@...aro.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Tingwei Zhang <quic_tingweiz@...cinc.com>,
Yuanfang Zhang <quic_yuanfang@...cinc.com>,
Trilok Soni <quic_tsoni@...cinc.com>,
Hao Zhang <quic_hazha@...cinc.com>,
linux-arm-msm@...r.kernel.org, bjorn.andersson@...aro.org,
Tao Zhang <taozha@....qualcomm.com>
Subject: Re: [PATCH v2 6/9] coresight-tpdm: Add node to set dsb programming
mode
On 19/01/2023 07:41, Tao Zhang wrote:
> Add node to set and show programming mode for TPDM DSB subunit.
> Once the DSB programming mode is set, it will be written to the
> register DSB_CR. Bit[10:9] of the DSB_CR register is used to set
> the DSB test mode.
>
> Signed-off-by: Tao Zhang <quic_taozha@...cinc.com>
> Signed-off-by: Tao Zhang <taozha@....qualcomm.com>
> ---
> drivers/hwtracing/coresight/coresight-tpdm.c | 45 +++++++++++++++++++++++++++-
> drivers/hwtracing/coresight/coresight-tpdm.h | 12 ++++++++
> 2 files changed, 56 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
> index 1dbb6c4..9126a37 100644
> --- a/drivers/hwtracing/coresight/coresight-tpdm.c
> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
> @@ -4,6 +4,7 @@
> */
>
> #include <linux/amba/bus.h>
> +#include <linux/bitfield.h>
> #include <linux/bitmap.h>
> #include <linux/coresight.h>
> #include <linux/coresight-pmu.h>
> @@ -38,7 +39,7 @@ static umode_t tpdm_dsb_is_visible(struct kobject *kobj,
>
> static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
> {
> - u32 val;
> + u32 val, mode;
>
> val = readl_relaxed(drvdata->base + TPDM_DSB_TIER);
> /* Set trigger timestamp */
> @@ -58,6 +59,19 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
>
> /* Set the enable bit of DSB control register to 1 */
> val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
> + /* Set the cycle accurate mode */
> + mode = TPDM_DSB_MODE_CYCACC(drvdata->dsb->mode);
> + val &= ~TPDM_DSB_TEST_MODE;
> + val |= FIELD_PREP(TPDM_DSB_TEST_MODE, mode);
> + /* Set the byte lane for high-performance mode */
> + mode = TPDM_DSB_MODE_HPBYTESEL(drvdata->dsb->mode);
> + val &= ~TPDM_DSB_HPSEL;
> + val |= FIELD_PREP(TPDM_DSB_HPSEL, mode);
> + /* Set the performance mode */
> + if (drvdata->dsb->mode & TPDM_DSB_MODE_PERF)
> + val |= TPDM_DSB_MODE;
> + else
> + val &= ~TPDM_DSB_MODE;
This looks a bit tricky to me. Please could you add documentation of
the values supported under Documentation/ABI/testing/sysfs-....-
Couldn't we provide separate handles for these "mode bits" ?
cycacc
perf
hpsel
Suzuki
> val |= TPDM_DSB_CR_ENA;
> writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
> }
> @@ -257,6 +271,34 @@ static struct attribute_group tpdm_attr_grp = {
> .attrs = tpdm_attrs,
> };
>
> +static ssize_t dsb_mode_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +
> + return sysfs_emit(buf, "%lx\n",
> + (unsigned long)drvdata->dsb->mode);
> +}
> +
> +static ssize_t dsb_mode_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t size)
> +{
> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + unsigned long val;
> +
> + if ((kstrtoul(buf, 0, &val)) || val < 0)
> + return -EINVAL;
> +
> + spin_lock(&drvdata->spinlock);
> + drvdata->dsb->mode = val & TPDM_MODE_ALL;
> + spin_unlock(&drvdata->spinlock);
> + return size;
> +}
> +static DEVICE_ATTR_RW(dsb_mode);
> +
> static ssize_t dsb_trig_type_show(struct device *dev,
> struct device_attribute *attr,
> char *buf)
> @@ -327,6 +369,7 @@ static ssize_t dsb_trig_ts_store(struct device *dev,
> }
> static DEVICE_ATTR_RW(dsb_trig_ts);
> static struct attribute *tpdm_dsb_attrs[] = {
> + &dev_attr_dsb_mode.attr,
> &dev_attr_dsb_trig_ts.attr,
> &dev_attr_dsb_trig_type.attr,
> NULL,
> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
> index 3ad1be5..b3ecb9f 100644
> --- a/drivers/hwtracing/coresight/coresight-tpdm.h
> +++ b/drivers/hwtracing/coresight/coresight-tpdm.h
> @@ -19,6 +19,16 @@
> #define TPDM_DSB_XTRIG_TSENAB BIT(1)
> /* Enable bit for DSB subunit trigger type */
> #define TPDM_DSB_TRIG_TYPE BIT(12)
> +/* Enable bit for DSB subunit perfmance mode */
> +#define TPDM_DSB_MODE BIT(1)
> +
> +/* DSB programming modes */
> +#define TPDM_DSB_MODE_CYCACC(val) (val & GENMASK(2, 0))
> +#define TPDM_DSB_MODE_PERF BIT(3)
> +#define TPDM_DSB_MODE_HPBYTESEL(val) (val & GENMASK(8, 4))
> +#define TPDM_MODE_ALL (0xFFFFFFF)
> +#define TPDM_DSB_TEST_MODE GENMASK(11, 9)
> +#define TPDM_DSB_HPSEL GENMASK(6, 2)
>
> /* TPDM integration test registers */
> #define TPDM_ITATBCNTRL (0xEF0)
> @@ -48,10 +58,12 @@
>
> /**
> * struct dsb_dataset - specifics associated to dsb dataset
> + * @mode: DSB programming mode
> * @trig_ts: Enable/Disable trigger timestamp.
> * @trig_type: Enable/Disable trigger type.
> */
> struct dsb_dataset {
> + u32 mode;
> bool trig_ts;
> bool trig_type;
> };
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