linux-kernel - Re: [PATCH v3 4/7] dt-bindings: Add RISC-V misaligned access performance

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Message-ID: <20230228145709.GA3198794-robh@kernel.org>
Date:   Tue, 28 Feb 2023 08:57:09 -0600
From:   Rob Herring <robh@...nel.org>
To:     Conor Dooley <conor@...nel.org>
Cc:     Evan Green <evan@...osinc.com>,
        Palmer Dabbelt <palmer@...osinc.com>, heiko@...ech.de,
        slewis@...osinc.com, vineetg@...osinc.com,
        Albert Ou <aou@...s.berkeley.edu>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v3 4/7] dt-bindings: Add RISC-V misaligned access
 performance

On Mon, Feb 27, 2023 at 10:57:55PM +0000, Conor Dooley wrote:
> Hey Evan,
> 
> On Tue, Feb 21, 2023 at 11:08:55AM -0800, Evan Green wrote:
> > From: Palmer Dabbelt <palmer@...osinc.com>
> > 
> > This key allows device trees to specify the performance of misaligned
> > accesses to main memory regions from each CPU in the system.
> 
> Could you fold some of Palmer's explanation for why this must be in the
> devicetree? Think this is where he explained it:
> https://lore.kernel.org/all/mhng-8736b349-e27a-4372-81ca-3a25d2ec1e94@palmer-ri-x1c9/

I still don't think this belongs in DT and replied on the above thread.

Rob