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Message-ID: <5d99c731-c47a-c525-76e5-4578d9dfc9ee@redhat.com>
Date: Tue, 28 Feb 2023 16:55:41 +0100
From: David Hildenbrand <david@...hat.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: linux-kernel@...r.kernel.org,
Andrew Morton <akpm@...ux-foundation.org>,
Hugh Dickins <hughd@...gle.com>,
John Hubbard <jhubbard@...dia.com>,
Jason Gunthorpe <jgg@...dia.com>,
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Yang Shi <shy828301@...il.com>,
Vlastimil Babka <vbabka@...e.cz>,
Nadav Amit <namit@...are.com>,
Andrea Arcangeli <aarcange@...hat.com>,
Peter Xu <peterx@...hat.com>, linux-mm@...ck.org,
x86@...nel.org, linux-alpha@...r.kernel.org,
linux-snps-arc@...ts.infradead.org,
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Michal Simek <monstr@...str.eu>
Subject: Re: [PATCH mm-unstable v1 11/26] microblaze/mm: support
__HAVE_ARCH_PTE_SWP_EXCLUSIVE
On 27.02.23 20:46, Geert Uytterhoeven wrote:
> Hi David,
>
> On Mon, Feb 27, 2023 at 6:01 PM David Hildenbrand <david@...hat.com> wrote:
>>>>>> /*
>>>>>> * Externally used page protection values.
>>>>>> diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
>>>>>> index 42f5988e998b..7e3de54bf426 100644
>>>>>> --- a/arch/microblaze/include/asm/pgtable.h
>>>>>> +++ b/arch/microblaze/include/asm/pgtable.h
>
>>>>>> * - All other bits of the PTE are loaded into TLBLO without
>>>>>> * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
>>>>>> * software PTE bits. We actually use bits 21, 24, 25, and
>>>>>> @@ -155,6 +155,9 @@ extern pte_t *va_to_pte(unsigned long address);
>>>>>> #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
>>>>>> #define _PMD_PRESENT PAGE_MASK
>>>>>>
>>>>>> +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */
>>>>>> +#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY
>>>>>
>>>>> _PAGE_DIRTY is 0x80, so this is also bit 7, thus the new comment is
>>>>> wrong?
>>>>
>>>> In the example, I use MSB-0 bit numbering (which I determined to be
>>>> correct in microblaze context eventually, but I got confused a couple a
>>>> times because it's very inconsistent). That should be MSB-0 bit 24.
>>>
>>> Thanks, TIL microblaze uses IBM bit numbering...
>>
>> I assume IBM bit numbering corresponds to MSB-0 bit numbering, correct?
>
> Correct, as seen in s370 and PowerPC manuals...
Good, I have some solid s390x background, but thinking about the term
"IBM PC" made me double-check that we're talking about the same thing ;)
>
>> I recall that I used the comment above "/* Definitions for MicroBlaze.
>> */" as an orientation.
>>
>> 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
>> RPN..................... 0 0 EX WR ZSEL....... W I M G
>
> Indeed, that's where I noticed the "unconventional" numbering...
>
>> So ... either we adjust both or we leave it as is. (again, depends on
>> what the right thing to to is -- which I don't know :) )
>
> It depends whether you want to match the hardware documentation,
> or the Linux BIT() macro and friends...
The hardware documentation, so we should be good.
Thanks!
--
Thanks,
David / dhildenb
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