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Message-Id: <1e69e526-c270-49a0-bf00-8418d1aed121@app.fastmail.com>
Date:   Tue, 28 Feb 2023 17:55:33 +0100
From:   "Arnd Bergmann" <arnd@...db.de>
To:     "Manivannan Sadhasivam" <manivannan.sadhasivam@...aro.org>,
        "Bjorn Andersson" <andersson@...nel.org>
Cc:     "Konrad Dybcio" <konrad.dybcio@...aro.org>,
        "Rob Herring" <robh+dt@...nel.org>,
        krzysztof.kozlowski+dt@...aro.org, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 01/16] arm64: dts: qcom: sdm845: Fix the PCI I/O port range

On Tue, Feb 28, 2023, at 17:47, Manivannan Sadhasivam wrote:
> For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
> located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
> (0x60200000, 0x40200000) specified in the ranges property for I/O region.
> -			ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
> -				 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
> +			ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
> +				 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
> 

This fixes the offset, but I wonder if the size of the I/O
window should be changed as well. The normal size is 64KB
(0x10000) per bus or less, while this one has 1MB.

It's probably harmless since each device would only use
a few bytes, and most devices don't need any I/O ports
at all.

     Arnd

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