lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CE9D5D21-63D3-40B8-BC71-11F1A5A93F7E@zytor.com>
Date:   Tue, 28 Feb 2023 16:02:00 -0800
From:   "H. Peter Anvin" <hpa@...or.com>
To:     David Woodhouse <dwmw2@...radead.org>,
        Brian Gerst <brgerst@...il.com>
CC:     Thomas Gleixner <tglx@...utronix.de>,
        Usama Arif <usama.arif@...edance.com>, kim.phillips@....com,
        piotrgorski@...hyos.org, oleksandr@...alenko.name,
        arjan@...ux.intel.com, mingo@...hat.com, bp@...en8.de,
        dave.hansen@...ux.intel.com, x86@...nel.org, pbonzini@...hat.com,
        paulmck@...nel.org, linux-kernel@...r.kernel.org,
        kvm@...r.kernel.org, rcu@...r.kernel.org, mimoja@...oja.de,
        hewenliang4@...wei.com, thomas.lendacky@....com, seanjc@...gle.com,
        pmenzel@...gen.mpg.de, fam.zheng@...edance.com,
        punit.agrawal@...edance.com, simon.evans@...edance.com,
        liangma@...ngbit.com
Subject: Re: [PATCH v12 07/11] x86/smpboot: Remove early_gdt_descr on 64-bit

On February 28, 2023 3:42:55 PM PST, David Woodhouse <dwmw2@...radead.org> wrote:
>
>
>On 28 February 2023 22:48:42 GMT, Brian Gerst <brgerst@...il.com> wrote:
>>On Tue, Feb 28, 2023 at 5:41 PM David Woodhouse <dwmw2@...radead.org> wrote:
>>>
>>> On Tue, 2023-02-28 at 21:57 +0000, David Woodhouse wrote:
>>> >
>>> > ----------------
>>> > IN:
>>> > 0xffffffffa20000b2:  48 31 d2                 xorq     %rdx, %rdx
>>> > 0xffffffffa20000b5:  48 8b 82 c0 74 d5 a3     movq     -0x5c2a8b40(%rdx), %rax
>>> > 0xffffffffa20000bc:  48 8b a0 58 14 00 00     movq     0x1458(%rax), %rsp
>>> > 0xffffffffa20000c3:  48 83 ec 10              subq     $0x10, %rsp
>>> > 0xffffffffa20000c7:  66 c7 04 24 7f 00        movw     $0x7f, (%rsp)
>>> > 0xffffffffa20000cd:  48 8d 82 00 10 81 a3     leaq     -0x5c7ef000(%rdx), %rax
>>> > 0xffffffffa20000d4:  48 89 44 24 02           movq     %rax, 2(%rsp)
>>> > 0xffffffffa20000d9:  0f 01 14 24              lgdtq    (%rsp)
>>> > 0xffffffffa20000dd:  48 83 c4 10              addq     $0x10, %rsp
>>> > 0xffffffffa20000e1:  31 c0                    xorl     %eax, %eax
>>> > 0xffffffffa20000e3:  8e d8                    movl     %eax, %ds
>>> >
>>> > I cannot work out where the value -0x5c7ef000 comes from, but it
>>> > doesn't seem to be the 0xb000 you claimed, and my brain is hurting
>>> > again...
>>>
>>> Turning off CONFIG_RANDOMIZE_BASE (or just looking at the vmlinux
>>> disassembly instead as Brian did) helps to resolve that FWIW.
>>>
>>> I've changed it to zero all of %rdx and pushed it back to the v12bis
>>> branch.
>>
>>xorl %edx, %edx is preferred, as a 32-bit operation zero-extends to
>>the full 64-bit register.  Using xorq to clear any of the lower 8
>>registers adds an unnecessary REX prefix.  Just one of many quirks of
>>the x86 instruction set...
>
>Ewww. Couldn't the assembler choose to omit the REX prefix then? It does more tricksy things than that already.
>
>I almost prefer having the prefix but (in the morning) if you prefer I can put it back as it was with a comment about the zero-extension.
>

Like it or not, that's how the assembler currently works.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ