lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20230301015702.3388458-5-peng.fan@oss.nxp.com>
Date:   Wed,  1 Mar 2023 09:56:57 +0800
From:   "Peng Fan (OSS)" <peng.fan@....nxp.com>
To:     herbert@...dor.apana.org.au, davem@...emloft.net,
        robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        horia.geanta@....com, pankaj.gupta@....com, gaurav.jain@....com,
        shawnguo@...nel.org, s.hauer@...gutronix.de
Cc:     kernel@...gutronix.de, stefan@...er.ch,
        linux-crypto@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        Peng Fan <peng.fan@....com>
Subject: [PATCH 4/9] dt-bindings: crypto: add fsl-sec4-snvs DT schema

From: Peng Fan <peng.fan@....com>

Convert fsl-sec4.txt SNVS RTC and PowerKey to DT schema

Signed-off-by: Peng Fan <peng.fan@....com>
---
 .../bindings/crypto/fsl-sec4-snvs.yaml        | 153 ++++++++++++++++++
 1 file changed, 153 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml

diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
new file mode 100644
index 000000000000..633e70f9b303
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/fsl-sec4-snvs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP SEC4 SNVS Binding
+
+description:
+  CONTENTS
+    -Secure Non-Volatile Storage (SNVS) Node
+    -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
+
+  Node defines address range and the associated interrupt for the SNVS
+  function.  This function monitors security state information & reports
+  security violations. This also included rtc, system power off and ON/OFF
+  key.
+
+  For more information on SEC4, ref fsl-sec4-crypto.yaml
+
+maintainers:
+  - Peng Fan <peng.fan@....com>
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: fsl,sec-v4.0-mon
+          - const: syscon
+
+  reg:
+    maxItems: 1
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  ranges:
+    description:
+      A standard property. Specifies the physical address range of the SNVS
+      register space.  A triplet that includes the child address, parent
+      address, & length.
+
+  interrupts:
+    description:
+      Specifies the interrupts generated by this device.  The value of the
+      interrupts property consists of one interrupt specifier. The format
+      of the specifier is defined by the binding document describing the
+      node's interrupt parent.
+    minItems: 1
+    maxItems: 2
+
+  snvs-rtc-lp:
+    type: object
+    description:
+      Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node. A SNVS
+      child node that defines SNVS LP RTC.
+
+    properties:
+      compatible:
+        enum:
+          - fsl,sec-v4.0-mon-rtc-lp
+
+      interrupts:
+        minItems: 1
+        maxItems: 2
+
+      regmap:
+        description: This is phandle to the register map node.
+        $ref: /schemas/types.yaml#/definitions/phandle
+
+      offset:
+        description: LP register offset. default it is 0x34.
+        $ref: /schemas/types.yaml#/definitions/uint32
+
+      clocks:
+        maxItems: 1
+
+      clock-names:
+        items:
+          - const: snvs-rtc
+
+    required:
+      - compatible
+      - interrupts
+      - regmap
+
+  snvs-powerkey:
+    type: object
+    description:
+      The snvs-pwrkey is designed to enable POWER key function which
+      controlled by SNVS ONOFF, the driver can report the status of POWER
+      key and wakeup system if pressed after system suspend.
+
+    properties:
+      compatible:
+        enum:
+          - fsl,sec-v4.0-pwrkey
+
+      interrupts:
+        description: The SNVS ON/OFF interrupt number to the CPU(s).
+        maxItems: 1
+
+      linux,keycode:
+        description: Keycode to emit, KEY_POWER by default.
+        $ref: /schemas/types.yaml#/definitions/int32
+
+      regmap:
+        description: This is phandle to the register map node.
+        $ref: /schemas/types.yaml#/definitions/phandle
+
+      wakeup-source:
+        description: Button can wake-up the system.
+        type: boolean
+
+    required:
+      - compatible
+      - interrupts
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/imx7d-clock.h>
+    sec_mon: sec_mon@...000 {
+        compatible = "fsl,sec-v4.0-mon", "syscon";
+        reg = <0x314000 0x1000>;
+
+        snvs-rtc-lp {
+            compatible = "fsl,sec-v4.0-mon-rtc-lp";
+            regmap = <&sec_mon>;
+            offset = <0x34>;
+            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&clks IMX7D_SNVS_CLK>;
+            clock-names = "snvs-rtc";
+        };
+
+        snvs-powerkey {
+            compatible = "fsl,sec-v4.0-pwrkey";
+            regmap = <&sec_mon>;
+            interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+            linux,keycode = <116>; /* KEY_POWER */
+            wakeup-source;
+        };
+    };
-- 
2.37.1

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ