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Message-ID: <66DC3D77-91AC-4F1B-BE3E-892A9B9980BC@zytor.com>
Date: Wed, 01 Mar 2023 09:16:54 -0800
From: "H. Peter Anvin" <hpa@...or.com>
To: "Maciej W. Rozycki" <macro@...am.me.uk>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>
CC: x86@...nel.org, linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PING^3][RESEND^3][PATCH v3] x86/PCI: Add support for the Intel 82378ZB/82379AB (SIO/SIO.A) PIRQ router
On March 1, 2023 5:14:59 AM PST, "Maciej W. Rozycki" <macro@...am.me.uk> wrote:
>On Sun, 8 Jan 2023, Maciej W. Rozycki wrote:
>
>> The Intel 82378ZB System I/O (SIO) and 82379AB System I/O APIC (SIO.A)
>> ISA bridges implement PCI interrupt steering with a PIRQ router[1][2]
>> that is exactly the same as that of the PIIX and ICH southbridges (or
>> actually the other way round, given that the SIO ASIC was there first).
>
> Ping for:
><https://lore.kernel.org/lkml/alpine.DEB.2.21.2301081956290.65308@angie.orcam.me.uk/>.
>
> I think the patch is fairly obvious. Are there any outstanding concerns
>that prevent it from being applied?
>
> Maciej
>
Has this patch been actually tested on a real machine, or is it purely theoretical?
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