linux-kernel - Re: [PATCH v3 12/34] loongarch: Implement the new page table range API

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <277cd2a7-9550-2ed6-1b66-a2e6612a2565@xen0n.name>
Date:   Wed, 1 Mar 2023 10:04:54 +0800
From:   WANG Xuerui <kernel@...0n.name>
To:     "Matthew Wilcox (Oracle)" <willy@...radead.org>,
        linux-mm@...ck.org, linux-arch@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org, Huacai Chen <chenhuacai@...nel.org>,
        loongarch@...ts.linux.dev
Subject: Re: [PATCH v3 12/34] loongarch: Implement the new page table range
 API

Hi,

On 3/1/23 05:37, Matthew Wilcox (Oracle) wrote:
> Add set_ptes() and update_mmu_cache_range().  It would probably be
> more efficient to implement __update_tlb() by flushing the entire
> folio instead of calling it __update_tlb() N times, but I'll leave
> that for someone who understands the architecture better.
Thanks for the patch! Unfortunately it doesn't seem possible 
architecture-wise to batch-flush pages right now on loongarch, but AFAIK 
the vendor *could* be listening so a future model could have the feature 
supported... who knows!
>
> Signed-off-by: Matthew Wilcox (Oracle) <willy@...radead.org>
> Cc: Huacai Chen <chenhuacai@...nel.org>
> Cc: WANG Xuerui <kernel@...0n.name>
> Cc: loongarch@...ts.linux.dev
> ---
>   arch/loongarch/include/asm/cacheflush.h |  2 ++
>   arch/loongarch/include/asm/pgtable.h    | 30 +++++++++++++++++++------
>   2 files changed, 25 insertions(+), 7 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/cacheflush.h b/arch/loongarch/include/asm/cacheflush.h
> index 0681788eb474..7907eb42bfbd 100644
> --- a/arch/loongarch/include/asm/cacheflush.h
> +++ b/arch/loongarch/include/asm/cacheflush.h
> @@ -47,8 +47,10 @@ void local_flush_icache_range(unsigned long start, unsigned long end);
>   #define flush_cache_vmap(start, end)			do { } while (0)
>   #define flush_cache_vunmap(start, end)			do { } while (0)
>   #define flush_icache_page(vma, page)			do { } while (0)
> +#define flush_icache_pages(vma, page)			do { } while (0)
>   #define flush_icache_user_page(vma, page, addr, len)	do { } while (0)
>   #define flush_dcache_page(page)				do { } while (0)
> +#define flush_dcache_folio(folio)			do { } while (0)
This will break the build because the surrounding code is unnecessarily 
redefining the stubs that the asm-generic include at the end of the file 
will properly take care of. With the build fixed (patch attached below), 
I can successfully boot-test and stress mm for a while on a Loongson 
3A5000. I haven't done the benchmarks though.
>   #define flush_dcache_mmap_lock(mapping)			do { } while (0)
>   #define flush_dcache_mmap_unlock(mapping)		do { } while (0)
>   
> <snip>

Cleanup patch:

-- >8 --

 From 0de3f49e6ba23c1b45e7b5da355f87398c4a7feb Mon Sep 17 00:00:00 2001
From: WANG Xuerui <git@...0n.name>
Date: Wed, 1 Mar 2023 09:32:18 +0800
Subject: [PATCH] LoongArch: Remove stub definitions in cacheflush.h

Per the current best practice in mm, it's unnecessary to define no-op
stubs explicitly in arch code, because the asm-generic inclusion at the
end of the file will properly take care of these. And the definition of
ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE to 0 is going to confuse the
asm-generic code, so remove the stubs for clarity and avoiding misuse.

Signed-off-by: WANG Xuerui <git@...0n.name>
---
  arch/loongarch/include/asm/cacheflush.h | 15 ---------------
  1 file changed, 15 deletions(-)

diff --git a/arch/loongarch/include/asm/cacheflush.h b/arch/loongarch/include/asm/cacheflush.h
index 326ac6f1b27c..cb8c046b4f17 100644
--- a/arch/loongarch/include/asm/cacheflush.h
+++ b/arch/loongarch/include/asm/cacheflush.h
@@ -37,21 +37,6 @@ void local_flush_icache_range(unsigned long start, unsigned long end);
  #define flush_icache_range     local_flush_icache_range
  #define flush_icache_user_range        local_flush_icache_range
  
-#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
-
-#define flush_cache_all()                              do { } while (0)
-#define flush_cache_mm(mm)                             do { } while (0)
-#define flush_cache_dup_mm(mm)                         do { } while (0)
-#define flush_cache_range(vma, start, end)             do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn)             do { } while (0)
-#define flush_cache_vmap(start, end)                   do { } while (0)
-#define flush_cache_vunmap(start, end)                 do { } while (0)
-#define flush_icache_user_page(vma, page, addr, len)   do { } while (0)
-#define flush_dcache_page(page)                                do { } while (0)
-#define flush_dcache_folio(folio)                      do { } while (0)
-#define flush_dcache_mmap_lock(mapping)                        do { } while (0)
-#define flush_dcache_mmap_unlock(mapping)              do { } while (0)
-
  #define cache_op(op, addr)                                             \
         __asm__ __volatile__(                                           \
         "       cacop   %0, %1                                  \n"     \

-- 
WANG "xen0n" Xuerui

Linux/LoongArch mailing list: https://lore.kernel.org/loongarch/