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Message-ID: <CAA8EJprbMybV0o1-436yLhVnnEX6qywrj=JmWDCL5usaH0DXiQ@mail.gmail.com>
Date: Thu, 2 Mar 2023 18:22:44 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Varadarajan Narayanan <quic_varada@...cinc.com>
Cc: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 7/8] arm64: dts: qcom: ipq9574: Add USB related nodes
On Thu, 2 Mar 2023 at 11:57, Varadarajan Narayanan
<quic_varada@...cinc.com> wrote:
>
> Add USB phy and controller related nodes
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
> ---
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 92 +++++++++++++++++++++++++++++++++++
> 1 file changed, 92 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 2bb4053..319b5bd 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -215,6 +215,98 @@
> #size-cells = <1>;
> ranges = <0 0 0 0xffffffff>;
>
> + ssphy_0: ssphy@...00 {
> + compatible = "qcom,ipq9574-qmp-usb3-phy";
> + reg = <0x7D000 0x1C4>;
> + #clock-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_USB0_AUX_CLK>,
> + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
> + clock-names = "aux", "cfg_ahb";
> +
> + resets = <&gcc GCC_USB0_PHY_BCR>,
> + <&gcc GCC_USB3PHY_0_PHY_BCR>;
> + reset-names = "phy","common";
> + status = "disabled";
> +
> + usb0_ssphy: lane@...00 {
Please use newer style device bindings for new PHYs.
> + reg = <0x0007D200 0x130>, /* Tx */
> + <0x0007D400 0x200>, /* Rx */
> + <0x0007D800 0x1F8>, /* PCS */
> + <0x0007D600 0x044>; /* PCS misc */
> + #phy-cells = <0>;
> + clocks = <&gcc GCC_USB0_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "gcc_usb0_pipe_clk_src";
No, this clock doesn't originate from gcc, so the gcc prefix is incorrect.
> + };
> + };
> +
> + qusb_phy_0: qusb@...00 {
> + compatible = "qcom,ipq9574-qusb2-phy";
> + reg = <0x07B000 0x180>;
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> + <&xo_board_clk>;
> + clock-names = "cfg_ahb", "ref";
> +
> + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> + status = "disabled";
> + };
> +
> + usb3: usb3@...0000 {
You know the drill. This node is in the wrong place.
> + compatible = "qcom,dwc3";
> + reg = <0x8AF8800 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_SNOC_USB_CLK>,
> + <&gcc GCC_ANOC_USB_AXI_CLK>,
> + <&gcc GCC_USB0_MASTER_CLK>,
> + <&gcc GCC_USB0_SLEEP_CLK>,
> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> +
> + clock-names = "sys_noc_axi",
> + "anoc_axi",
> + "master",
> + "sleep",
> + "mock_utmi";
Please fix the indentation of the lists.
> +
> + assigned-clocks = <&gcc GCC_SNOC_USB_CLK>,
> + <&gcc GCC_ANOC_USB_AXI_CLK>,
Why do you assign clock rates to the NOC clocks? Should they be set
using the interconnect instead?
> + <&gcc GCC_USB0_MASTER_CLK>,
> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> + assigned-clock-rates = <200000000>,
> + <200000000>,
> + <200000000>,
> + <24000000>;
> +
> + resets = <&gcc GCC_USB_BCR>;
> + status = "disabled";
> +
> + dwc_0: dwc3@...0000 {
> + compatible = "snps,dwc3";
> + reg = <0x8A00000 0xcd00>;
> + clock-names = "ref";
> + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
clocks before clock-names
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&qusb_phy_0>, <&usb0_ssphy>;
> + phy-names = "usb2-phy", "usb3-phy";
> + tx-fifo-resize;
> + snps,dis_ep_cache_eviction;
> + snps,is-utmi-l1-suspend;
> + snps,hird-threshold = /bits/ 8 <0x0>;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_u3_susphy_quirk;
> + snps,quirk-frame-length-adjustment = <0x0A87F0A0>;
> + dr_mode = "host";
> + };
> + };
> +
> pcie0_phy: phy@...00 {
> compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> reg = <0x00084000 0x1bc>; /* Serdes PLL */
> --
> 2.7.4
>
--
With best wishes
Dmitry
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