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Date: Fri, 3 Mar 2023 13:47:53 -0800
From: Jacob Pan <jacob.jun.pan@...ux.intel.com>
To: "Tian, Kevin" <kevin.tian@...el.com>
Cc: LKML <linux-kernel@...r.kernel.org>,
"iommu@...ts.linux.dev" <iommu@...ts.linux.dev>,
Jason Gunthorpe <jgg@...dia.com>,
Lu Baolu <baolu.lu@...ux.intel.com>,
Joerg Roedel <joro@...tes.org>,
"dmaengine@...r.kernel.org" <dmaengine@...r.kernel.org>,
"vkoul@...nel.org" <vkoul@...nel.org>,
Robin Murphy <robin.murphy@....com>,
Will Deacon <will@...nel.org>,
"David Woodhouse" <dwmw2@...radead.org>,
"Raj, Ashok" <ashok.raj@...el.com>,
"Liu, Yi L" <yi.l.liu@...el.com>,
"Yu, Fenghua" <fenghua.yu@...el.com>,
"Jiang, Dave" <dave.jiang@...el.com>,
"Luck, Tony" <tony.luck@...el.com>,
"Zanussi, Tom" <tom.zanussi@...el.com>,
jacob.jun.pan@...ux.intel.com
Subject: Re: [PATCH 3/4] iommu/sva: Support reservation of global PASIDs
Hi Kevin,
On Thu, 2 Mar 2023 09:43:03 +0000, "Tian, Kevin" <kevin.tian@...el.com>
wrote:
> > From: Jacob Pan <jacob.jun.pan@...ux.intel.com>
> > Sent: Thursday, March 2, 2023 9:00 AM
> >
> > Global PASID allocation is under IOMMU SVA code since it is the primary
> > use case. However, some architecture such as VT-d, global PASIDs are
> > necessary for its internal use of DMA API with PASID.
>
> No, global PASID is not a VT-d restriction. It's from ENQCMD/S hence a
> device requirement.
I meant VT-d based platforms, it is kind of intertwined in that ENQCMDS
does not restrict RIDPASID!=DMA PASID, vt-d does. Without this
restriction, there wouldn't be a need for this patch. Let me reword.
> >
> > This patch introduces SVA APIs to reserve and release global PASIDs.
> >
> > Link: https://lore.kernel.org/all/20230301235646.2692846-4-
> > jacob.jun.pan@...ux.intel.com/
> > Signed-off-by: Jacob Pan <jacob.jun.pan@...ux.intel.com>
> > ---
> > drivers/iommu/iommu-sva.c | 25 +++++++++++++++++++++++++
> > include/linux/iommu.h | 14 ++++++++++++++
> > 2 files changed, 39 insertions(+)
> >
> > diff --git a/drivers/iommu/iommu-sva.c b/drivers/iommu/iommu-sva.c
> > index 8c92a145e15d..cfdeafde88a9 100644
> > --- a/drivers/iommu/iommu-sva.c
> > +++ b/drivers/iommu/iommu-sva.c
> > @@ -149,6 +149,31 @@ u32 iommu_sva_get_pasid(struct iommu_sva
> > *handle)
> > }
> > EXPORT_SYMBOL_GPL(iommu_sva_get_pasid);
> >
> > +ioasid_t iommu_sva_reserve_pasid(ioasid_t min, ioasid_t max)
> > +{
> > + int ret;
> > +
> > + if (min == IOMMU_PASID_INVALID || max ==
> > IOMMU_PASID_INVALID ||
> > + min == 0 || max < min)
> > + return IOMMU_PASID_INVALID;
> > +
> > + ret = ida_alloc_range(&iommu_global_pasid_ida, min, max,
> > GFP_KERNEL);
> > + if (ret < 0)
> > + return IOMMU_PASID_INVALID;
> > +
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(iommu_sva_reserve_pasid);
> > +
>
> I'm not sure it's the right way. It's not related to SVA.
>
> We should move iommu_global_pasid_ida to iomm.c and then have
> another interface for allocation.
>
> Above is pretty generic so probably a general one like:
>
> ioasid_t iommu_allocate_global_pasid(struct device *dev)
>
> internally it can use [1, dev->iommu->max_pasids] as min/max instead
> of passed in from the caller.
sounds good to me, will do.
Thanks,
Jacob
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