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Date: Fri, 3 Mar 2023 11:17:26 +0800
From: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
To: Matthias Brugger <matthias.bgg@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Stephen Boyd <sboyd@...nel.org>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
CC: <Project_Global_Chrome_Upstream_Group@...iatek.com>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>, <hsinyi@...omium.org>,
Allen-KH Cheng <allen-kh.cheng@...iatek.com>
Subject: [PATCH v3 5/7] arm64: dts: mediatek: mt8186: Add audio controller node
Add audio controller node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 62 ++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 337bcf3c1571..f198fd8abc1d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1046,6 +1046,68 @@
};
};
+ afe: audio-controller@...10000 {
+ compatible = "mediatek,mt8186-sound";
+ reg = <0 0x11210000 0 0x2000>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>,
+ <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>,
+ <&topckgen CLK_TOP_AUDIO>,
+ <&topckgen CLK_TOP_AUD_INTBUS>,
+ <&topckgen CLK_TOP_MAINPLL_D2_D4>,
+ <&topckgen CLK_TOP_AUD_1>,
+ <&apmixedsys CLK_APMIXED_APLL1>,
+ <&topckgen CLK_TOP_AUD_2>,
+ <&apmixedsys CLK_APMIXED_APLL2>,
+ <&topckgen CLK_TOP_AUD_ENGEN1>,
+ <&topckgen CLK_TOP_APLL1_D8>,
+ <&topckgen CLK_TOP_AUD_ENGEN2>,
+ <&topckgen CLK_TOP_APLL2_D8>,
+ <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>,
+ <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>,
+ <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV0>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV1>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV2>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV4>,
+ <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>,
+ <&topckgen CLK_TOP_AUDIO_H>,
+ <&clk26m>;
+ clock-names = "aud_infra_clk",
+ "mtkaif_26m_clk",
+ "top_mux_audio",
+ "top_mux_audio_int",
+ "top_mainpll_d2_d4",
+ "top_mux_aud_1",
+ "top_apll1_ck",
+ "top_mux_aud_2",
+ "top_apll2_ck",
+ "top_mux_aud_eng1",
+ "top_apll1_d8",
+ "top_mux_aud_eng2",
+ "top_apll2_d8",
+ "top_i2s0_m_sel",
+ "top_i2s1_m_sel",
+ "top_i2s2_m_sel",
+ "top_i2s4_m_sel",
+ "top_tdm_m_sel",
+ "top_apll12_div0",
+ "top_apll12_div1",
+ "top_apll12_div2",
+ "top_apll12_div4",
+ "top_apll12_div_tdm",
+ "top_mux_audio_h",
+ "top_clk26m_clk";
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ mediatek,infracfg = <&infracfg_ao>;
+ mediatek,topckgen = <&topckgen>;
+ resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>;
+ reset-names = "audiosys";
+ status = "disabled";
+ };
+
mmc0: mmc@...30000 {
compatible = "mediatek,mt8186-mmc",
"mediatek,mt8183-mmc";
--
2.18.0
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