| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20230306153222.157667-19-manivannan.sadhasivam@linaro.org>
Date: Mon, 6 Mar 2023 21:02:21 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: andersson@...nel.org, lpieralisi@...nel.org, kw@...ux.com,
krzysztof.kozlowski+dt@...aro.org, robh@...nel.org
Cc: konrad.dybcio@...aro.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org, quic_srichara@...cinc.com,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Subject: [PATCH 18/19] arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes
The "mhi" region contains the debug registers that could be used to monitor
the PCIe link transitions.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 0d02599d8867..5c7f40345992 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1650,11 +1650,12 @@ pcie4: pcie@...0000 {
device_type = "pci";
compatible = "qcom,pcie-sc8280xp";
reg = <0x0 0x01c00000 0x0 0x3000>,
+ <0x0 0x01c03000 0x0 0x1000>,
<0x0 0x30000000 0x0 0xf1d>,
<0x0 0x30000f20 0x0 0xa8>,
<0x0 0x30001000 0x0 0x1000>,
<0x0 0x30100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ reg-names = "parf", "mhi", "dbi", "elbi", "atu", "config";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>,
@@ -1749,11 +1750,12 @@ pcie3b: pcie@...8000 {
device_type = "pci";
compatible = "qcom,pcie-sc8280xp";
reg = <0x0 0x01c08000 0x0 0x3000>,
+ <0x0 0x01c0b000 0x0 0x1000>,
<0x0 0x32000000 0x0 0xf1d>,
<0x0 0x32000f20 0x0 0xa8>,
<0x0 0x32001000 0x0 0x1000>,
<0x0 0x32100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ reg-names = "parf", "mhi", "dbi", "elbi", "atu", "config";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>,
@@ -1846,11 +1848,12 @@ pcie3a: pcie@...0000 {
device_type = "pci";
compatible = "qcom,pcie-sc8280xp";
reg = <0x0 0x01c10000 0x0 0x3000>,
+ <0x0 0x01c13000 0x0 0x1000>,
<0x0 0x34000000 0x0 0xf1d>,
<0x0 0x34000f20 0x0 0xa8>,
<0x0 0x34001000 0x0 0x1000>,
<0x0 0x34100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ reg-names = "parf", "mhi", "dbi", "elbi", "atu", "config";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>,
@@ -1946,11 +1949,12 @@ pcie2b: pcie@...8000 {
device_type = "pci";
compatible = "qcom,pcie-sc8280xp";
reg = <0x0 0x01c18000 0x0 0x3000>,
+ <0x0 0x01c1b000 0x0 0x1000>,
<0x0 0x38000000 0x0 0xf1d>,
<0x0 0x38000f20 0x0 0xa8>,
<0x0 0x38001000 0x0 0x1000>,
<0x0 0x38100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ reg-names = "parf", "mhi", "dbi", "elbi", "atu", "config";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>,
@@ -2043,11 +2047,12 @@ pcie2a: pcie@...0000 {
device_type = "pci";
compatible = "qcom,pcie-sc8280xp";
reg = <0x0 0x01c20000 0x0 0x3000>,
+ <0x0 0x01c23000 0x0 0x1000>,
<0x0 0x3c000000 0x0 0xf1d>,
<0x0 0x3c000f20 0x0 0xa8>,
<0x0 0x3c001000 0x0 0x1000>,
<0x0 0x3c100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ reg-names = "parf", "mhi", "dbi", "elbi", "atu", "config";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
--
2.25.1
Powered by blists - more mailing lists