linux-kernel - [v5 PATCH 1/7] crypto: stm32

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Message-Id: <E1pZ2ff-000e0r-EU@formenos.hmeau.com>
Date:   Mon, 06 Mar 2023 12:41:59 +0800
From:   "Herbert Xu" <herbert@...dor.apana.org.au>
To:     Linus Walleij <linus.walleij@...aro.org>,
        Lionel Debieve <lionel.debieve@...s.st.com>,
        Li kunyu <kunyu@...china.com>, davem@...emloft.net,
        linux-arm-kernel@...ts.infradead.org, linux-crypto@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        linux-stm32@...md-mailman.stormreply.com, mcoquelin.stm32@...il.com
Subject: [v5 PATCH 1/7] crypto: stm32 - Save 54 CSR registers

The CSR registers go from 0 to 53.  So the number of registers
should be 54.

Reviewed-by: Linus Walleij <linus.walleij@...aro.org>
Tested-by: Linus Walleij <linus.walleij@...aro.org>
Signed-off-by: Herbert Xu <herbert@...dor.apana.org.au>
---

 drivers/crypto/stm32/stm32-hash.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/stm32/stm32-hash.c b/drivers/crypto/stm32/stm32-hash.c
index 7bf805563ac2..bde2b40a6a32 100644
--- a/drivers/crypto/stm32/stm32-hash.c
+++ b/drivers/crypto/stm32/stm32-hash.c
@@ -68,7 +68,7 @@
 #define HASH_MASK_DATA_INPUT		BIT(1)
 
 /* Context swap register */
-#define HASH_CSR_REGISTER_NUMBER	53
+#define HASH_CSR_REGISTER_NUMBER	54
 
 /* Status Flags */
 #define HASH_SR_DATA_INPUT_READY	BIT(0)