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Message-ID: <CAK9=C2XAOKbyrbOnDP1GzW1VyO-f-V-oEVcp+PhGHeHKFh4C6A@mail.gmail.com>
Date: Mon, 6 Mar 2023 22:03:19 +0530
From: Anup Patel <apatel@...tanamicro.com>
To: Alexandre Ghiti <alexghiti@...osinc.com>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Rob Herring <robh+dt@...nel.org>,
Frank Rowand <frowand.list@...il.com>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v6 0/2] riscv: Use PUD/P4D/PGD pages for the linear mapping
On Wed, Mar 1, 2023 at 1:56 PM Alexandre Ghiti <alexghiti@...osinc.com> wrote:
>
> This patchset intends to improve tlb utilization by using hugepages for
> the linear mapping.
>
> base-commit-tag: v6.2-rc7
>
> v6:
> - quiet LLVM warning by casting phys_ram_base into an unsigned long
>
> v5:
> - Fix nommu builds by getting rid of riscv_pfn_base in patch 1, thanks
> Conor
> - Add RB from Andrew
>
> v4:
> - Rebase on top of v6.2-rc3, as noted by Conor
> - Add Acked-by Rob
>
> v3:
> - Change the comment about initrd_start VA conversion so that it fits
> ARM64 and RISCV64 (and others in the future if needed), as suggested
> by Rob
>
> v2:
> - Add a comment on why RISCV64 does not need to set initrd_start/end that
> early in the boot process, as asked by Rob
>
> Alexandre Ghiti (2):
> riscv: Get rid of riscv_pfn_base variable
> riscv: Use PUD/P4D/PGD pages for the linear mapping
I tried this series but it is getting stuck after reaching user space.
Does this series require some other dependent patches ?
Regards,
Anup
>
> arch/riscv/include/asm/page.h | 19 +++++++++++++++++--
> arch/riscv/mm/init.c | 28 ++++++++++++++++++----------
> arch/riscv/mm/physaddr.c | 16 ++++++++++++++++
> drivers/of/fdt.c | 11 ++++++-----
> 4 files changed, 57 insertions(+), 17 deletions(-)
>
> --
> 2.37.2
>
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