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Message-Id: <1678080302-29691-6-git-send-email-quic_rohiagar@quicinc.com>
Date: Mon, 6 Mar 2023 10:55:01 +0530
From: Rohit Agarwal <quic_rohiagar@...cinc.com>
To: agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
lee@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, mani@...nel.org,
lpieralisi@...nel.org, kw@...ux.com, bhelgaas@...gle.com,
manivannan.sadhasivam@...aro.org
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
Rohit Agarwal <quic_rohiagar@...cinc.com>
Subject: [PATCH 5/6] ARM: dts: qcom: sdx65-mtp: Enable PCIE0 PHY
Enable PCIE0 PHY on SDX65 MTP for PCIE EP.
Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
---
arch/arm/boot/dts/qcom-sdx65-mtp.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
index 85ea02d..86bb853 100644
--- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -245,6 +245,13 @@
status = "okay";
};
+&pcie0_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l1b_1p2>;
+ vdda-pll-supply = <&vreg_l4b_0p88>;
+};
+
&qpic_bam {
status = "okay";
};
--
2.7.4
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