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Message-Id: <20230303-arm64-cpufeature-helpers-v1-2-b16cf36acaea@kernel.org>
Date: Mon, 06 Mar 2023 22:20:24 +0000
From: Mark Brown <broonie@...nel.org>
To: Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>
Cc: Suzuki K Poulose <suzuki.poulose@....com>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Mark Brown <broonie@...nel.org>
Subject: [PATCH 2/3] arm64/cpufeature: Consistently use symbolic constants
for min_field_value
A number of the cpufeatures use raw numbers for the minimum field values
specified rather than symbolic constants. In preparation for the use of
helper macros replace all these with the appropriate constants.
No change in the generated binary.
Signed-off-by: Mark Brown <broonie@...nel.org>
---
arch/arm64/kernel/cpufeature.c | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 77862b7c8908..1002ac437e8b 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2217,7 +2217,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.field_pos = ID_AA64PFR0_EL1_GIC_SHIFT,
.field_width = 4,
.sign = FTR_UNSIGNED,
- .min_field_value = 1,
+ .min_field_value = ID_AA64PFR0_EL1_GIC_IMP,
},
{
.desc = "Enhanced Counter Virtualization",
@@ -2228,7 +2228,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.field_pos = ID_AA64MMFR0_EL1_ECV_SHIFT,
.field_width = 4,
.sign = FTR_UNSIGNED,
- .min_field_value = 1,
+ .min_field_value = ID_AA64MMFR0_EL1_ECV_IMP,
},
#ifdef CONFIG_ARM64_PAN
{
@@ -2240,7 +2240,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT,
.field_width = 4,
.sign = FTR_UNSIGNED,
- .min_field_value = 1,
+ .min_field_value = ID_AA64MMFR1_EL1_PAN_IMP,
.cpu_enable = cpu_enable_pan,
},
#endif /* CONFIG_ARM64_PAN */
@@ -2254,7 +2254,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT,
.field_width = 4,
.sign = FTR_UNSIGNED,
- .min_field_value = 3,
+ .min_field_value = ID_AA64MMFR1_EL1_PAN_PAN3,
},
#endif /* CONFIG_ARM64_EPAN */
#ifdef CONFIG_ARM64_LSE_ATOMICS
@@ -2267,7 +2267,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.field_pos = ID_AA64ISAR0_EL1_ATOMIC_SHIFT,
.field_width = 4,
.sign = FTR_UNSIGNED,
- .min_field_value = 2,
+ .min_field_value = ID_AA64ISAR0_EL1_ATOMIC_IMP,
},
#endif /* CONFIG_ARM64_LSE_ATOMICS */
{
@@ -2335,7 +2335,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.sys_reg = SYS_ID_AA64PFR0_EL1,
.field_pos = ID_AA64PFR0_EL1_CSV3_SHIFT,
.field_width = 4,
- .min_field_value = 1,
+ .min_field_value = ID_AA64PFR0_EL1_CSV3_IMP,
.matches = unmap_kernel_at_el0,
.cpu_enable = kpti_install_ng_mappings,
},
@@ -2355,7 +2355,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.sys_reg = SYS_ID_AA64ISAR1_EL1,
.field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT,
.field_width = 4,
- .min_field_value = 1,
+ .min_field_value = ID_AA64ISAR1_EL1_DPB_IMP,
},
{
.desc = "Data cache clean to Point of Deep Persistence",
@@ -2366,7 +2366,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.sign = FTR_UNSIGNED,
.field_pos = ID_AA64ISAR1_EL1_DPB_SHIFT,
.field_width = 4,
- .min_field_value = 2,
+ .min_field_value = ID_AA64ISAR1_EL1_DPB_DPB2,
},
#endif
#ifdef CONFIG_ARM64_SVE
@@ -2437,7 +2437,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.sign = FTR_UNSIGNED,
.field_pos = ID_AA64MMFR2_EL1_FWB_SHIFT,
.field_width = 4,
- .min_field_value = 1,
+ .min_field_value = ID_AA64MMFR2_EL1_FWB_IMP,
.matches = has_cpuid_feature,
},
{
@@ -2448,7 +2448,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.sign = FTR_UNSIGNED,
.field_pos = ID_AA64MMFR2_EL1_TTL_SHIFT,
.field_width = 4,
- .min_field_value = 1,
+ .min_field_value = ID_AA64MMFR2_EL1_TTL_IMP,
.matches = has_cpuid_feature,
},
{
@@ -2478,7 +2478,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.sign = FTR_UNSIGNED,
.field_pos = ID_AA64MMFR1_EL1_HAFDBS_SHIFT,
.field_width = 4,
- .min_field_value = 2,
+ .min_field_value = ID_AA64MMFR1_EL1_HAFDBS_DBM,
.matches = has_hw_dbm,
.cpu_enable = cpu_enable_hw_dbm,
},
@@ -2491,7 +2491,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.sys_reg = SYS_ID_AA64ISAR0_EL1,
.field_pos = ID_AA64ISAR0_EL1_CRC32_SHIFT,
.field_width = 4,
- .min_field_value = 1,
+ .min_field_value = ID_AA64ISAR0_EL1_CRC32_IMP,
},
{
.desc = "Speculative Store Bypassing Safe (SSBS)",
@@ -2514,7 +2514,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.sign = FTR_UNSIGNED,
.field_pos = ID_AA64MMFR2_EL1_CnP_SHIFT,
.field_width = 4,
- .min_field_value = 1,
+ .min_field_value = ID_AA64MMFR2_EL1_CnP_IMP,
.cpu_enable = cpu_enable_cnp,
},
#endif
@@ -2527,7 +2527,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.field_pos = ID_AA64ISAR1_EL1_SB_SHIFT,
.field_width = 4,
.sign = FTR_UNSIGNED,
- .min_field_value = 1,
+ .min_field_value = ID_AA64ISAR1_EL1_SB_IMP,
},
#ifdef CONFIG_ARM64_PTR_AUTH
{
@@ -2636,7 +2636,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.field_width = 4,
.field_pos = ID_AA64MMFR2_EL1_E0PD_SHIFT,
.matches = has_cpuid_feature,
- .min_field_value = 1,
+ .min_field_value = ID_AA64MMFR2_EL1_E0PD_IMP,
.cpu_enable = cpu_enable_e0pd,
},
#endif
@@ -2649,7 +2649,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.field_pos = ID_AA64ISAR0_EL1_RNDR_SHIFT,
.field_width = 4,
.sign = FTR_UNSIGNED,
- .min_field_value = 1,
+ .min_field_value = ID_AA64ISAR0_EL1_RNDR_IMP,
},
#ifdef CONFIG_ARM64_BTI
{
@@ -2703,7 +2703,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.field_pos = ID_AA64ISAR1_EL1_LRCPC_SHIFT,
.field_width = 4,
.matches = has_cpuid_feature,
- .min_field_value = 1,
+ .min_field_value = ID_AA64ISAR1_EL1_LRCPC_IMP,
},
#ifdef CONFIG_ARM64_SME
{
--
2.30.2
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