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Message-ID: <f8669264-0c96-0337-2293-4d215e313b93@arinc9.com>
Date: Mon, 6 Mar 2023 16:19:18 +0300
From: Arınç ÜNAL <arinc.unal@...nc9.com>
To: Sean Wang <sean.wang@...iatek.com>,
Landen Chao <Landen.Chao@...iatek.com>,
DENG Qingfang <dqfext@...il.com>, Andrew Lunn <andrew@...n.ch>,
Florian Fainelli <f.fainelli@...il.com>,
Vladimir Oltean <olteanv@...il.com>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
Russell King <linux@...linux.org.uk>
Cc: Russell King <rmk+kernel@...linux.org.uk>,
René van Dorst <opensource@...rst.com>,
Alexander Couzens <lynxis@...0.eu>,
Ilya Lipnitskiy <ilya.lipnitskiy@...il.com>,
Richard van Schagen <richard@...terhints.com>,
Frank Wunderlich <frank-w@...lic-files.de>,
erkin.bozoglu@...ont.com, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org
Subject: Re: [RFC PATCH net] net: dsa: mt7530: move PLL setup out of port 6
pad configuration
On 4.03.2023 15:54, arinc9.unal@...il.com wrote:
> From: Arınç ÜNAL <arinc.unal@...nc9.com>
>
> Move the PLL setup of the MT7530 switch out of the pad configuration of
> port 6 to mt7530_setup, after reset.
>
> This fixes the improper initialisation of the switch when only port 5 is
> used as a CPU port.
>
> Add supported phy modes of port 5 on the PLL setup.
>
> Remove now incorrect comment regarding P5 as GMAC5.
>
> Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
> Fixes: 38f790a80560 ("net: dsa: mt7530: Add support for port 5")
> Signed-off-by: Arınç ÜNAL <arinc.unal@...nc9.com>
> ---
>
> I'm trying to mimic this change by Alexander [0] for the MT7530 switch.
> This is already the case for MT7530 and MT7531 on the MediaTek ethernet
> driver on U-Boot [1] [2].
>
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=42bc4fafe359ed6b73602b7a2dba0dd99588f8ce
> [1] https://github.com/u-boot/u-boot/blob/a94ab561e2f49a80d8579930e840b810ab1a1330/drivers/net/mtk_eth.c#L729
> [2] https://github.com/u-boot/u-boot/blob/a94ab561e2f49a80d8579930e840b810ab1a1330/drivers/net/mtk_eth.c#L903
>
> There are some parts I couldn't figure out myself with my limited C
> knowledge. I've pointed them out on the code. Vladimir, could you help?
>
> There is a lot of code which is only needed for port 6 or trgmii on port 6,
> but runs whether port 6 or trgmii is used or not. For now, the best I can
> do is to fix port 5 so it works without port 6 being used.
>
> The U-Boot driver seems to be much more organised so it could be taken as
> a reference to sort out this DSA driver further.
>
> Also, now that the pad setup for mt7530 is also moved somewhere else, can
> we completely get rid of @pad_setup?
>
> Arınç
>
> ---
> drivers/net/dsa/mt7530.c | 46 +++++++++++++++++++++++++++++-----------
> 1 file changed, 34 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
> index 0e99de26d159..fb20ce4f443e 100644
> --- a/drivers/net/dsa/mt7530.c
> +++ b/drivers/net/dsa/mt7530.c
> @@ -395,9 +395,8 @@ mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
>
> /* Setup TX circuit including relevant PAD and driving */
> static int
> -mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
> +mt7530_pad_clk_setup(struct mt7530_priv *priv, phy_interface_t interface)
> {
> - struct mt7530_priv *priv = ds->priv;
> u32 ncpo1, ssc_delta, trgint, i, xtal;
>
> xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
> @@ -409,9 +408,32 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
> return -EINVAL;
> }
>
> + /* Is setting trgint to 0 really needed for the !trgint check? */
> + trgint = 0;
> +
> + /* FIXME: run this switch if p5 is defined on the devicetree */
> + /* and change interface to the phy-mode of port 5 */
> + switch (interface) {
> + case PHY_INTERFACE_MODE_GMII:
> + /* PLL frequency: 125MHz */
> + ncpo1 = 0x0c80;
> + break;
> + case PHY_INTERFACE_MODE_MII:
> + break;
> + case PHY_INTERFACE_MODE_RGMII:
> + /* PLL frequency: 125MHz */
> + ncpo1 = 0x0c80;
> + break;
> + default:
> + dev_err(priv->dev, "xMII interface %d not supported\n",
> + interface);
> + return -EINVAL;
> + }
> +
> + /* FIXME: run this switch if p6 is defined on the devicetree */
> + /* and change interface to the phy-mode of port 6 */
> switch (interface) {
> case PHY_INTERFACE_MODE_RGMII:
> - trgint = 0;
> /* PLL frequency: 125MHz */
> ncpo1 = 0x0c80;
> break;
> @@ -2172,7 +2194,11 @@ mt7530_setup(struct dsa_switch *ds)
> SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
> SYS_CTRL_REG_RST);
>
> - /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
> + /* Setup switch core pll */
> + /* FIXME: feed the phy-mode of port 5 and 6, if the ports are defined on the devicetree */
> + mt7530_pad_clk_setup(priv, interface);
Unlike mt7531_pll_setup, there are return codes on mt7530_pad_clk_setup
so we may need to check for the return code here.
Arınç
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