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Message-ID: <ZAX1r1xXgnJ7fwIX@hovoldconsulting.com>
Date: Mon, 6 Mar 2023 15:16:15 +0100
From: Johan Hovold <johan@...nel.org>
To: Abel Vesa <abel.vesa@...aro.org>
Cc: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Sai Prakash Ranjan <quic_saipraka@...cinc.com>,
Juerg Haefliger <juerg.haefliger@...onical.com>,
linux-arm-msm@...r.kernel.org,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
stable@...r.kernel.org
Subject: Re: [PATCH v3] soc: qcom: llcc: Fix slice configuration values for
SC8280XP
On Mon, Mar 06, 2023 at 03:57:52PM +0200, Abel Vesa wrote:
> On 23-03-06 14:01:20, Johan Hovold wrote:
> > On Sun, Feb 19, 2023 at 06:57:01PM +0200, Abel Vesa wrote:
> > > The slice IDs for CVPFW, CPUSS1 and CPUWHT currently overflow the 32bit
> > > LLCC config registers. Fix that by using the slice ID values taken from
> > > the latest LLCC SC table.
> >
> > This still doesn't really explain what the impact of this bug is (e.g.
> > for people doing backports), but I guess this will do.
> >
>
> Sent a v4 here:
> https://lore.kernel.org/all/20230306135527.509796-1-abel.vesa@linaro.org/
Looks good, thanks!
Johan
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