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Message-ID: <6d5ea6d8-d8c6-0875-f0b3-2fcaac64899d@quicinc.com> Date: Mon, 6 Mar 2023 20:03:41 +0530 From: Md Sadre Alam <quic_mdalam@...cinc.com> To: Boris Brezillon <boris.brezillon@...labora.com> CC: <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>, <linux-mtd@...ts.infradead.org>, <linux-arm-msm@...r.kernel.org>, <robh+dt@...nel.org>, <vigneshr@...com>, <richard@....at>, <miquel.raynal@...tlin.com>, <agross@...nel.org>, <bjorn.andersson@...aro.org>, <quic_srichara@...cinc.com>, <qpic_varada@...cinc.com>, <quic_sjaganat@...cinc.com> Subject: Re: [PATCH 2/5] mtd: rawnand: qcom: Add initial support for qspi nand On 3/6/2023 7:45 PM, Md Sadre Alam wrote: > > On 10/29/2020 2:37 PM, Boris Brezillon wrote: >> Hello, >> >> On Sat, 10 Oct 2020 11:01:39 +0530 >> Md Sadre Alam <mdalam@...eaurora.org> wrote: >> >>> This change will add initial support for qspi (serial nand). >>> >>> QPIC Version v.2.0 onwards supports serial nand as well so this >>> change will initialize all required register to enable qspi (serial >>> nand). >>> >>> This change is supporting very basic functionality of qspi nand flash. >>> >>> 1. Reset device (Reset QSPI NAND device). >>> >>> 2. Device detection (Read id QSPI NAND device). >> Unfortunately, that's not going to work in the long term. You're >> basically hacking the raw NAND framework to make SPI NANDs fit. I do >> understand the rationale behind this decision (re-using the code for >> ECC and probably other things), but that's not going to work. So I'd >> recommend doing the following instead: >> >> 1/ implement a SPI-mem controller driver >> 2/ implement an ECC engine driver so the ECC logic can be shared >> between the SPI controller and raw NAND controller drivers >> 3/ convert the raw NAND driver to the exec_op() interface (none of >> this hack would have been possible if the driver was using the new >> API) >> >> Regards, >> >> Boris >> > Sorry for late reply, again started working on this feature > support. The QPIC v2 on wards there is serial nand support got added > , its not a standard SPI controller > > its QPIC controller having support for serial nand. All SPI related > configuration done by QPIC hardware and its not exposed as SPI bus to > the external world. Only based on > > QPIC_SPI_CFG = 1, serial functionality will get selected. So that > no need to implement as SPI-mem controller driver, since its not a SPI > controller. > > Please check the below diagram for top view of QPIC controller. > > ___________________________________________________________________________ | QPIC wrapper | AHB master IF | |_______________________ __________________________ | <------------------------------------------------- | | QPIC | | QPIC_IO_MACRO | |--------------------------------------------->Serial NAND IOs | | QPIC_SPI_CFG = 1 ----> | | (Control SPI Bus internally) | |---------------------------------------------> | | | | | | | | | | | | | | | |__________________________| | | | | _ ___________________________ | | | | | Ebi2_ext_if | | | | QPIC_SPI_CFG=0 -------> | | | |-------------------------------------------------> | | | | | |-------------------------------------------------->Parallel NAND IOs <---------------------------------------------------- | |________________________ | | __________________________| | AHB Slav IF | | |_____________________________________________________________________________| > > > > Regards, > > Alam. > > >>
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