linux-kernel - Re: [PATCH v3 8/9] arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port

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Message-ID: <49f2efcf-da1b-051e-6396-a6f4f0b9a97a@linaro.org>
Date:   Mon, 6 Mar 2023 15:59:06 +0100
From:   Konrad Dybcio <konrad.dybcio@...aro.org>
To:     Bartosz Golaszewski <brgl@...ev.pl>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc:     linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
Subject: Re: [PATCH v3 8/9] arm64: dts: qcom: sa8775p-ride: enable the GNSS
 UART port



On 16.02.2023 13:52, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
> 
> Enable the high-speed UART port connected to the GNSS controller on the
> sa8775p-adp development board.
> 
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
> ---
>  arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 34 +++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> index d01ca3a9ee37..6f96907b335c 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
> @@ -13,6 +13,7 @@ / {
>  
>  	aliases {
>  		serial0 = &uart10;
> +		serial1 = &uart12;
>  		i2c18 = &i2c18;
>  		spi16 = &spi16;
>  	};
> @@ -66,6 +67,30 @@ qup_i2c18_default: qup-i2c18-state {
>  		drive-strength = <2>;
>  		bias-pull-up;
>  	};
> +
qup_uart12_default: [...] {
    qup_uart12_cts: [...]
};

[...]

pinctrl-0 = <&qup_uart12_default>;

?

Konrad
> +	qup_uart12_cts: qup-uart12-cts-state {
> +		pins = "gpio52";
> +		function = "qup1_se5";
> +		bias-disable;
> +	};
> +
> +	qup_uart12_rts: qup-uart12-rts-state {
> +		pins = "gpio53";
> +		function = "qup1_se5";
> +		bias-pull-down;
> +	};
> +
> +	qup_uart12_tx: qup-uart12-tx-state {
> +		pins = "gpio54";
> +		function = "qup1_se5";
> +		bias-pull-up;
> +	};
> +
> +	qup_uart12_rx: qup-uart12-rx-state {
> +		pins = "gpio55";
> +		function = "qup1_se5";
> +		bias-pull-down;
> +	};
>  };
>  
>  &uart10 {
> @@ -75,6 +100,15 @@ &uart10 {
>  	status = "okay";
>  };
>  
> +&uart12 {
> +	pinctrl-0 = <&qup_uart12_cts>,
> +		    <&qup_uart12_rts>,
> +		    <&qup_uart12_tx>,
> +		    <&qup_uart12_rx>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
>  &xo_board_clk {
>  	clock-frequency = <38400000>;
>  };