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Message-ID: <18a73c95-53da-9acb-9e10-0e6095e7dd31@intel.com>
Date: Tue, 7 Mar 2023 14:50:08 -0700
From: Dave Jiang <dave.jiang@...el.com>
To: Bjorn Helgaas <helgaas@...nel.org>, Vinod Koul <vkoul@...nel.org>
Cc: dmaengine@...r.kernel.org, linux-kernel@...r.kernel.org,
Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: [PATCH] dmaengine: ioat: use PCI core macros for PCIe Capability
On 3/7/23 2:46 PM, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <bhelgaas@...gle.com>
>
> The PCIe Capability is defined by the PCIe spec, so use the PCI_EXP_DEVCTL
> macros defined by the PCI core instead of defining copies in IOAT. This
> makes it easier to find all uses of the PCIe Device Control register. No
> functional change intended.
>
> Signed-off-by: Bjorn Helgaas <bhelgaas@...gle.com>
Acked-by: Dave Jiang <dave.jiang@...el.com>
> ---
> drivers/dma/ioat/init.c | 6 +++---
> drivers/dma/ioat/registers.h | 7 -------
> 2 files changed, 3 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/dma/ioat/init.c b/drivers/dma/ioat/init.c
> index 5d707ff63554..fa7c0f9aa61d 100644
> --- a/drivers/dma/ioat/init.c
> +++ b/drivers/dma/ioat/init.c
> @@ -1191,13 +1191,13 @@ static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca)
> ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base);
>
> /* disable relaxed ordering */
> - err = pcie_capability_read_word(pdev, IOAT_DEVCTRL_OFFSET, &val16);
> + err = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &val16);
> if (err)
> return pcibios_err_to_errno(err);
>
> /* clear relaxed ordering enable */
> - val16 &= ~IOAT_DEVCTRL_ROE;
> - err = pcie_capability_write_word(pdev, IOAT_DEVCTRL_OFFSET, val16);
> + val16 &= ~PCI_EXP_DEVCTL_RELAX_EN;
> + err = pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, val16);
> if (err)
> return pcibios_err_to_errno(err);
>
> diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h
> index f55a5f92f185..54cf0ad39887 100644
> --- a/drivers/dma/ioat/registers.h
> +++ b/drivers/dma/ioat/registers.h
> @@ -14,13 +14,6 @@
> #define IOAT_PCI_CHANERR_INT_OFFSET 0x180
> #define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184
>
> -/* PCIe config registers */
> -
> -/* EXPCAPID + N */
> -#define IOAT_DEVCTRL_OFFSET 0x8
> -/* relaxed ordering enable */
> -#define IOAT_DEVCTRL_ROE 0x10
> -
> /* MMIO Device Registers */
> #define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */
>
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