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Message-ID: <d3761f4a-6945-9a7e-03e9-bf0279c6f0f2@redhat.com>
Date: Tue, 7 Mar 2023 12:02:12 +0100
From: Hans de Goede <hdegoede@...hat.com>
To: Jithu Joseph <jithu.joseph@...el.com>, markgross@...nel.org
Cc: tglx@...utronix.de, mingo@...hat.com, bp@...en8.de,
dave.hansen@...ux.intel.com, x86@...nel.org, hpa@...or.com,
gregkh@...uxfoundation.org, rostedt@...dmis.org,
ashok.raj@...el.com, tony.luck@...el.com,
linux-kernel@...r.kernel.org, platform-driver-x86@...r.kernel.org,
patches@...ts.linux.dev, ravi.v.shankar@...el.com,
thiago.macieira@...el.com, athenas.jimenez.gonzalez@...el.com,
sohil.mehta@...el.com
Subject: Re: [PATCH v3 0/8] Add Array BIST test support to IFS
Hi Jithu,
On 3/1/23 02:59, Jithu Joseph wrote:
> Changes in v3
> - GregKH
> - Separating read-only fields from rw fields in
> struct ifs_device (patch 1/8)
> - Remove the subdirectory intel_ifs/<n> for devicenode (patch 2/8)
> - Replaced an enum with #define (patch 4/8)
> - Dave Hansen
> - Remove tracing patch
> - ifs_array_test_core() (patch 6/8)
> - fix an initialization bug
> - other suggested changes
> - Use basic types in ifs_array for first two fields. (kept
> the union to avoid type castings)
Thank you for the new version. Given all the feedback on
the previous 2 versions I'm going to wait a bit to see if more
feedback comes in before reviewing this myself.
Regards,
Hans
> v2 submission:
> Link: https://lore.kernel.org/lkml/20230214234426.344960-1-jithu.joseph@intel.com/
>
> Changes in v2
> - remove duplicate initializations from ifs_array_test_core()
> (Dave Hansen, patch 4/7)
> - remove bit parsing from tracing fast path to tracing
> output (Steven Rostedt, patch 5/7)
> - move "ATTRIBUTE_GROUPS(plat_ifs_array)" to core.c and remove
> exporting function ifs_get_array_groups() (Greg KH, patch 3/7)
> - Generalized doc and ABI doc (Greg KH, patches 6/7 and 7/7)
>
> v1 submission:
> Link: https://lore.kernel.org/lkml/20230131234302.3997223-1-jithu.joseph@intel.com/
>
> Array BIST is a new type of core test introduced under the Intel Infield
> Scan (IFS) suite of tests.
>
> Emerald Rapids (EMR) is the first CPU to support Array BIST.
> Array BIST performs tests on some portions of the core logic such as
> caches and register files. These are different portions of the silicon
> compared to the parts tested by Scan at Field (SAF).
>
> Unlike SAF, Array BIST doesn't require any test content to be loaded.
>
> Jithu Joseph (8):
> platform/x86/intel/ifs: Reorganize driver data
> platform/x86/intel/ifs: IFS cleanup
> x86/include/asm/msr-index.h: Add IFS Array test bits
> platform/x86/intel/ifs: Introduce Array Scan test to IFS
> platform/x86/intel/ifs: Sysfs interface for Array BIST
> platform/x86/intel/ifs: Implement Array BIST test
> platform/x86/intel/ifs: Update IFS doc
> Documentation/ABI: Update IFS ABI doc
>
> arch/x86/include/asm/msr-index.h | 2 +
> drivers/platform/x86/intel/ifs/ifs.h | 62 +++++++++----
> drivers/platform/x86/intel/ifs/core.c | 92 ++++++++++++++-----
> drivers/platform/x86/intel/ifs/load.c | 8 +-
> drivers/platform/x86/intel/ifs/runtest.c | 91 +++++++++++++++++-
> drivers/platform/x86/intel/ifs/sysfs.c | 17 ++--
> .../ABI/testing/sysfs-platform-intel-ifs | 8 +-
> 7 files changed, 221 insertions(+), 59 deletions(-)
>
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