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Message-ID: <08aa9325-ed36-250c-d4d6-de6af1e82de5@linaro.org>
Date:   Tue, 7 Mar 2023 14:39:59 +0100
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Linus Walleij <linus.walleij@...aro.org>
Cc:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
        linux-arm-msm@...r.kernel.org, linux-gpio@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] dt-bindings: pinctrl: qcom: lpass-lpi: correct
 description of second reg

On 07/03/2023 14:32, Linus Walleij wrote:
> On Thu, Mar 2, 2023 at 4:52 PM Krzysztof Kozlowski
> <krzysztof.kozlowski@...aro.org> wrote:
> 
>> The description of second IO address is a bit confusing.  It is supposed
>> to be the MCC range which contains the slew rate registers, not the slew
>> rate register base.  The Linux driver then accesses slew rate register
>> with hard-coded offset (0xa000).
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> 
> LGTM, is this something I should just apply or will you collect a larger
> series of Qcom DT patches this time around as well?

Please grab it. I think I cleaned up Qualcomm pinctrl bindings from
technical debt, thus no more work for me!

Best regards,
Krzysztof

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