linux-kernel - Re: [PATCH 2/2] arm64: dts: qcom: sm8450: Mark UFS controller as cache coherent

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Message-ID: <b2a8a0ca-02b1-f792-a6ee-51f98ea615b0@linaro.org>
Date:   Wed, 8 Mar 2023 09:11:26 +0100
From:   Neil Armstrong <neil.armstrong@...aro.org>
To:     Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
        andersson@...nel.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org
Cc:     konrad.dybcio@...aro.org, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8450: Mark UFS controller as
 cache coherent

On 07/03/2023 16:32, Manivannan Sadhasivam wrote:
> The UFS controller on SM8450 supports cache coherency, hence add the
> "dma-coherent" property to mark it as such.
> 
> Fixes: 07fa917a335e ("arm64: dts: qcom: sm8450: add ufs nodes")
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> ---
>   arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 1a744a33bcf4..3ef47b4e9af7 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -4003,6 +4003,7 @@ ufs_mem_hc: ufshc@...4000 {
>   			power-domains = <&gcc UFS_PHY_GDSC>;
>   
>   			iommus = <&apps_smmu 0xe0 0x0>;
> +			dma-coherent;
>   
>   			interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
>   					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;

Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>