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Message-ID: <20230308082800.3008-2-minda.chen@starfivetech.com>
Date: Wed, 8 Mar 2023 16:27:58 +0800
From: Minda Chen <minda.chen@...rfivetech.com>
To: Emil Renner Berthing <emil.renner.berthing@...onical.com>,
Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Pawel Laszczak <pawell@...ence.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Peter Chen <peter.chen@...nel.org>,
Roger Quadros <rogerq@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Conor Dooley <conor@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-phy@...ts.infradead.org>, <linux-usb@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>,
Minda Chen <minda.chen@...rfivetech.com>
Subject: [PATCH v2 1/3] dt-bindings: phy: Add StarFive JH7110 USB dt-binding
Add StarFive JH7110 SoC USB 3.0 phy dt-binding.
USB controller is cadence USB 3.0 IP.
Signed-off-by: Minda Chen <minda.chen@...rfivetech.com>
---
.../bindings/phy/starfive,jh7110-usb-phy.yaml | 158 ++++++++++++++++++
1 file changed, 158 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
new file mode 100644
index 000000000000..daa88d065deb
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
@@ -0,0 +1,158 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive USB 2.0 and 3.0 PHY
+
+maintainers:
+ - Minda Chen<minda.chen@...rfivetech.com>
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jh7110-usb
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: usb3
+ - const: usb2
+
+ clocks:
+ items:
+ - description: usb 125m clock
+ - description: app 125m clock
+ - description: lpm clock
+ - description: stb clock
+ - description: apb clock
+ - description: axi clock
+ - description: utmi apb clock
+
+ clock-names:
+ items:
+ - const: usb_125m
+ - const: usb0_app_125
+ - const: usb0_lpm
+ - const: usb0_stb
+ - const: usb0_apb
+ - const: usb0_axi
+ - const: usb0_utmi_apb
+
+ resets:
+ items:
+ - description: USB0_PWRUP reset
+ - description: USB0_APB reset
+ - description: USB0_AXI reset
+ - description: USB0_UTMI_APB reset
+
+ starfive,sys-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle to System Register Controller sys_syscon node.
+ - description: offset of SYS_SYSCONSAIF__SYSCFG register for USB.
+ description:
+ The phandle to System Register Controller syscon node and the offset
+ of SYS_SYSCONSAIF__SYSCFG register for USB.
+
+ starfive,stg-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle to System Register Controller stg_syscon node.
+ - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for USB.
+ - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for USB.
+ - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for USB.
+ - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for USB.
+ description:
+ The phandle to System Register Controller syscon node and the offset
+ of STG_SYSCONSAIF__SYSCFG register for USB. Total 4 regsisters offset
+ for USB.
+
+ dr_mode:
+ description: PHY mode.
+ enum:
+ - host
+ - peripheral
+ - otg
+
+ "#address-cells":
+ maximum: 2
+
+ "#size-cells":
+ maximum: 2
+
+ ranges: true
+
+ starfive,usb2-only:
+ type: boolean
+ description: Set USB using usb 2.0 phy. Supprt USB 2.0 only
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - resets
+ - starfive,sys-syscon
+ - starfive,stg-syscon
+ - dr_mode
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+patternProperties:
+ "^usb@[0-9a-f]+$":
+ type: object
+ description: |
+ usbphy node should have '1' usb controller subnode.
+ It could be Cadence USB3 DRD controller.
+ Cadence USB3 should follow the bindings specified in
+ Documentation/devicetree/bindings/usb/cdns,usb3.yaml
+
+additionalProperties: false
+
+examples:
+ - |
+ usbphy@...00000 {
+ compatible = "starfive,jh7110-usb";
+ reg = <0x10210000 0x1000>,
+ <0x10200000 0x1000>;
+ reg-names = "usb3", "usb2";
+ clocks = <&syscrg 95>,
+ <&stgcrg 6>,
+ <&stgcrg 4>,
+ <&stgcrg 5>,
+ <&stgcrg 1>,
+ <&stgcrg 3>,
+ <&stgcrg 2>;
+ clock-names = "usb_125m", "usb0_app_125", "usb0_lpm",
+ "usb0_stb", "usb0_apb", "usb0_axi", "usb0_utmi_apb";
+ resets = <&stgcrg 10>,
+ <&stgcrg 8>,
+ <&stgcrg 7>,
+ <&stgcrg 9>;
+ starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
+ starfive,sys-syscon = <&sys_syscon 0x18>;
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usb@...00000 {
+ compatible = "cdns,usb3";
+ reg = <0x10100000 0x10000>,
+ <0x10110000 0x10000>,
+ <0x10120000 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <100>, <108>, <110>;
+ interrupt-names = "host", "peripheral", "otg";
+ phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
+ maximum-speed = "super-speed";
+ };
+ };
--
2.17.1
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