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Message-ID: <811092b8-a83c-cd00-c965-1f7552d423eb@linaro.org>
Date: Wed, 8 Mar 2023 11:19:50 +0100
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
andersson@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org
Cc: konrad.dybcio@...aro.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: sm8550: Mark UFS controller as cache
coherent
On 08/03/2023 06:46, Manivannan Sadhasivam wrote:
> The UFS controller on SM8550 supports cache coherency, hence add the
> "dma-coherent" property to mark it as such.
>
> Fixes: 35cf1aaab169 ("arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes")
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index ff4d342c0725..5315e24fa525 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1905,6 +1905,7 @@ ufs_mem_hc: ufs@...4000 {
> required-opps = <&rpmhpd_opp_nom>;
>
> iommus = <&apps_smmu 0x60 0x0>;
> + dma-coherent;
>
> interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
> <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
Reviewed-by: Neil Armstrong <neil.armstrong@...aro.org>
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