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Message-Id: <1678277993-18836-6-git-send-email-quic_rohiagar@quicinc.com>
Date: Wed, 8 Mar 2023 17:49:52 +0530
From: Rohit Agarwal <quic_rohiagar@...cinc.com>
To: agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
lee@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, mani@...nel.org,
lpieralisi@...nel.org, kw@...ux.com, bhelgaas@...gle.com,
manivannan.sadhasivam@...aro.org
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
Rohit Agarwal <quic_rohiagar@...cinc.com>
Subject: [PATCH v2 5/6] ARM: dts: qcom: sdx65-mtp: Enable PCIe PHY
Enable PCIe PHY on SDX65 MTP for PCIe EP. While at it,
updating status as last property for each node.
Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
---
arch/arm/boot/dts/qcom-sdx65-mtp.dts | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
index ed98c83..facb8e2 100644
--- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -245,13 +245,18 @@
status = "okay";
};
-&qpic_bam {
+&pcie_phy {
+ vdda-phy-supply = <&vreg_l1b_1p2>;
+ vdda-pll-supply = <&vreg_l4b_0p88>;
+
status = "okay";
};
-&qpic_nand {
+&qpic_bam {
status = "okay";
+};
+&qpic_nand {
nand@0 {
reg = <0>;
@@ -262,11 +267,14 @@
secure-regions = /bits/ 64 <0x500000 0x500000
0xa00000 0xb00000>;
};
+
+ status = "okay";
};
&remoteproc_mpss {
- status = "okay";
memory-region = <&mpss_adsp_mem>;
+
+ status = "okay";
};
&usb {
@@ -278,14 +286,16 @@
};
&usb_hsphy {
- status = "okay";
vdda-pll-supply = <&vreg_l4b_0p88>;
vdda33-supply = <&vreg_l10b_3p08>;
vdda18-supply = <&vreg_l5b_1p8>;
+
+ status = "okay";
};
&usb_qmpphy {
- status = "okay";
vdda-phy-supply = <&vreg_l4b_0p88>;
vdda-pll-supply = <&vreg_l1b_1p2>;
+
+ status = "okay";
};
--
2.7.4
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