linux-kernel - [PATCH v1 09/25] arm64: dts: colibri-imx8x: Add separate pinctrl group for cs2

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Message-Id: <20230308125300.58244-10-dev@pschenker.ch>
Date:   Wed,  8 Mar 2023 13:52:43 +0100
From:   Philippe Schenker <dev@...henker.ch>
To:     devicetree@...r.kernel.org, Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>
Cc:     NXP Linux Team <linux-imx@....com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        Frank Rowand <frowand.list@...il.com>,
        linux-arm-kernel@...ts.infradead.org,
        Fabio Estevam <festevam@...il.com>,
        Philippe Schenker <philippe.schenker@...adex.com>,
        linux-kernel@...r.kernel.org
Subject: [PATCH v1 09/25] arm64: dts: colibri-imx8x: Add separate pinctrl group for cs2

From: Philippe Schenker <philippe.schenker@...adex.com>

Add a separate pinctrl group for chip-select 2 for Colibri SPI. That way
one is able to use it separately.

Signed-off-by: Philippe Schenker <philippe.schenker@...adex.com>
---

 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index d4d748a93afc..2cc94589c36f 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -120,7 +120,7 @@ &usdhc2 {
 &iomuxc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>,
-		    <&pinctrl_hog2>;
+		    <&pinctrl_hog2>, <&pinctrl_lpspi2_cs2>;
 
 	/* On-module touch pen-down interrupt */
 	pinctrl_ad7879_int: ad7879intgrp {
@@ -231,7 +231,6 @@ pinctrl_hog0: hog0grp {
 			   <IMX8QXP_CSI_D07_CI_PI_D09				0x61>,		/* SODIMM  65 */
 			   <IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00			0x20>,		/* SODIMM  96 */
 			   <IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03		0x06000020>,	/* SODIMM  85 */
-			   <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02		0x06000020>,	/* SODIMM  65 */
 			   <IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11		0x20>,		/* SODIMM  69 */
 			   <IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18		0x20>,		/* SODIMM  99 */
 			   <IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19		0x20>,		/* SODIMM 105 */
@@ -327,6 +326,10 @@ pinctrl_lpspi2: lpspi2grp {
 			   <IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO			0x06000040>;	/* SODIMM  92 */
 	};
 
+	pinctrl_lpspi2_cs2: lpspi2cs2grp {
+		fsl,pins = <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02		0x21>;		/* SODIMM  65 */
+	};
+
 	/* Colibri UART_B */
 	pinctrl_lpuart0: lpuart0grp {
 		fsl,pins = <IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B		0x06000020>,	/* SODIMM  34 */
-- 
2.39.2