linux-kernel - RE: [v5 PATCH 7/7] crypto: stm32 - Save and restore between each request

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Date:   Thu, 9 Mar 2023 22:19:44 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Linus Walleij' <linus.walleij@...aro.org>,
        Herbert Xu <herbert@...dor.apana.org.au>
CC:     Lionel Debieve <lionel.debieve@...s.st.com>,
        Li kunyu <kunyu@...china.com>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-crypto@...r.kernel.org" <linux-crypto@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-stm32@...md-mailman.stormreply.com" 
        <linux-stm32@...md-mailman.stormreply.com>,
        "mcoquelin.stm32@...il.com" <mcoquelin.stm32@...il.com>
Subject: RE: [v5 PATCH 7/7] crypto: stm32 - Save and restore between each
 request

From: Linus Walleij
> Sent: 09 March 2023 07:35
...
> But actually I think the bug will never trigger, because the datasheet
> for the DB8500 (Ux500) says this:
> 
> "Then the message can be sent, by writing it word per word into the
> HASH_DIN register.
> When a block of 512 bits, i.e. 16 words have been written, a partial
> digest computation will
> start upon writing the first data of the next block. The AHB bus will
> be busy for 82 cycles for
> SHA-1 algorithm (66 cycles for SHA-256 algorithm)."

What speed clock is that?

4 or 5 extra clocks/word may (or may not) be significant.

In terms of latency it may be noise compared to some PCIe
reads done by hardware interrupt handlers.
Some slow PCIe targets (like the fpga one we use) pretty
much take 1us to handle a read cycle.

	David

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