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Message-ID: <bc2680cb-e81f-4afb-5a8c-ac0f5a9aed78@quicinc.com>
Date:   Thu, 9 Mar 2023 10:17:17 +0530
From:   Kathiravan T <quic_kathirav@...cinc.com>
To:     Konrad Dybcio <konrad.dybcio@...aro.org>, <agross@...nel.org>,
        <andersson@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <mturquette@...libre.com>,
        <sboyd@...nel.org>, <catalin.marinas@....com>, <will@...nel.org>,
        <arnd@...db.de>, <dmitry.baryshkov@...aro.org>,
        <geert+renesas@...der.be>, <nfraprado@...labora.com>,
        <broonie@...nel.org>, <rafal@...ecki.pl>, <robimarko@...il.com>,
        <quic_gurus@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-clk@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH V6 7/9] dt-bindings: firmware: qcom,scm: document IPQ5332
 SCM


On 3/8/2023 9:14 PM, Konrad Dybcio wrote:
>
> On 8.03.2023 16:39, Kathiravan T wrote:
>> On 3/8/2023 4:31 PM, Konrad Dybcio wrote:
>>> On 7.03.2023 07:22, Kathiravan T wrote:
>>>> Document the compatible for IPQ5332 SCM.
>>>>
>>>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
>>>> Signed-off-by: Kathiravan T <quic_kathirav@...cinc.com>
>>>> ---
>>> Does this board not have a crypto engine / CE1 clock exposed via
>>> RPMCC? It will be enabled by default, but Linux should be aware
>>> of it, so that we don't gate it by accident.
>>
>> IPQ5332 doesn't have the crypto engine and also it doesn't have RPMCC. Sorry, could you please help to explain how it is related to SCM?
> SCM usually requires certain clocks to be up and that often includes
> the CE1 clock on fairly recent designs.


Thanks for the explanation. I don't see such requirements for this SoC.


> Konrad
>> Thanks, Kathiravan T.

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