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Message-ID: <DB6P189MB0568832655843F63CCE9B63C9CB59@DB6P189MB0568.EURP189.PROD.OUTLOOK.COM>
Date: Thu, 9 Mar 2023 09:42:54 +0000
From: David Binderman <dcb314@...mail.com>
To: Laurent Pinchart <laurent.pinchart@...asonboard.com>
CC: "andrzej.hajda@...el.com" <andrzej.hajda@...el.com>,
"neil.armstrong@...aro.org" <neil.armstrong@...aro.org>,
"rfoss@...nel.org" <rfoss@...nel.org>,
"jonas@...boo.se" <jonas@...boo.se>,
"jernej.skrabec@...il.com" <jernej.skrabec@...il.com>,
"airlied@...il.com" <airlied@...il.com>,
"daniel@...ll.ch" <daniel@...ll.ch>,
"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: drivers/gpu/drm/bridge/fsl-ldb.c:101: possible loss of
information.
Hello there Laurent,
>Would you be able to send a patch to fix this ?
Sadly, no. My success rate with kernel patches is low enough to make it not worth trying.
Regards
David Binderman
From: Laurent Pinchart <laurent.pinchart@...asonboard.com>
Sent: 09 March 2023 09:26
To: David Binderman <dcb314@...mail.com>
Cc: andrzej.hajda@...el.com <andrzej.hajda@...el.com>; neil.armstrong@...aro.org <neil.armstrong@...aro.org>; rfoss@...nel.org <rfoss@...nel.org>; jonas@...boo.se <jonas@...boo.se>; jernej.skrabec@...il.com <jernej.skrabec@...il.com>; airlied@...il.com <airlied@...il.com>; daniel@...ll.ch <daniel@...ll.ch>; dri-devel@...ts.freedesktop.org <dri-devel@...ts.freedesktop.org>; linux-kernel@...r.kernel.org <linux-kernel@...r.kernel.org>
Subject: Re: drivers/gpu/drm/bridge/fsl-ldb.c:101: possible loss of information.
Hi David,
On Thu, Mar 09, 2023 at 07:59:34AM +0000, David Binderman wrote:
> Hello there Laurent,
>
> >We could, but I don't think it will make any difference in practice as
> >the maximum pixel clock frequency supported by the SoC is 80MHz (per
> >LVDS channel). That would result in a 560MHz frequency returned by this
> >function, well below the 31 bits limit.
>
> Thanks for your explanation. I have a couple of suggestions for possible improvements:
>
> 1. Your explanatory text in a comment nearby. This helps all readers of the code.
>
> 2. Might the frequency go up to 300 MHz anytime soon ? The code will stop working then.
> In this case, I would suggest to put in a run time sanity check to make sure no 31 bit overflow.
As it's a hardware limit of the SoC, I wouldn't expect so.
This being said, I think adding a UL suffix to the constants would be
better than a comment as it will please static checkers and serve as
documentation to humans. Would you be able to send a patch to fix this ?
> Just a couple of ideas for the code.
Thanks for taking the time to share those.
--
Regards,
Laurent Pinchart
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