lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Thu, 9 Mar 2023 15:41:09 +0530
From:   Ravi Bangoria <ravi.bangoria@....com>
To:     <peterz@...radead.org>
CC:     <ravi.bangoria@....com>, <namhyung@...nel.org>,
        <eranian@...gle.com>, <acme@...nel.org>, <mark.rutland@....com>,
        <jolsa@...nel.org>, <irogers@...gle.com>, <bp@...en8.de>,
        <x86@...nel.org>, <linux-perf-users@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <sandipan.das@....com>,
        <ananth.narayan@....com>, <santosh.shukla@....com>
Subject: [PATCH v2 1/3] perf/ibs: Introduce ibs_core_pmu_event()

Split core pmu event comparing code from perf_ibs_precise_event() into
a separate function ibs_core_pmu_event().

Signed-off-by: Ravi Bangoria <ravi.bangoria@....com>
---
 arch/x86/events/amd/ibs.c         | 52 +++++++++++++++++--------------
 arch/x86/include/asm/perf_event.h |  2 ++
 2 files changed, 31 insertions(+), 23 deletions(-)

diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index 64582954b5f6..67eb5b7564e8 100644
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -218,29 +218,7 @@ static int perf_ibs_precise_event(struct perf_event *event, u64 *config)
 		return -EOPNOTSUPP;
 	}
 
-	switch (event->attr.type) {
-	case PERF_TYPE_HARDWARE:
-		switch (event->attr.config) {
-		case PERF_COUNT_HW_CPU_CYCLES:
-			*config = 0;
-			return 0;
-		}
-		break;
-	case PERF_TYPE_RAW:
-		switch (event->attr.config) {
-		case 0x0076:
-			*config = 0;
-			return 0;
-		case 0x00C1:
-			*config = IBS_OP_CNT_CTL;
-			return 0;
-		}
-		break;
-	default:
-		return -ENOENT;
-	}
-
-	return -EOPNOTSUPP;
+	return ibs_core_pmu_event(event, config);
 }
 
 static int perf_ibs_init(struct perf_event *event)
@@ -1296,6 +1274,34 @@ u32 get_ibs_caps(void)
 
 EXPORT_SYMBOL(get_ibs_caps);
 
+/* Convert core pmu event into IBS event */
+int ibs_core_pmu_event(struct perf_event *event, u64 *config)
+{
+	switch (event->attr.type) {
+	case PERF_TYPE_HARDWARE:
+		switch (event->attr.config) {
+		case PERF_COUNT_HW_CPU_CYCLES:
+			*config = 0;
+			return 0;
+		}
+		break;
+	case PERF_TYPE_RAW:
+		switch (event->attr.config) {
+		case 0x0076:
+			*config = 0;
+			return 0;
+		case 0x00C1:
+			*config = IBS_OP_CNT_CTL;
+			return 0;
+		}
+		break;
+	default:
+		return -ENOENT;
+	}
+
+	return -EOPNOTSUPP;
+}
+
 static inline int get_eilvt(int offset)
 {
 	return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 8fc15ed5e60b..1ad9d504ae71 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -475,8 +475,10 @@ struct pebs_xmm {
 
 #ifdef CONFIG_X86_LOCAL_APIC
 extern u32 get_ibs_caps(void);
+extern int ibs_core_pmu_event(struct perf_event *event, u64 *config);
 #else
 static inline u32 get_ibs_caps(void) { return 0; }
+static inline int ibs_core_pmu_event(struct perf_event *event, u64 *config) { return -ENOENT; }
 #endif
 
 #ifdef CONFIG_PERF_EVENTS
-- 
2.39.2

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ