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Message-ID: <4e426dc4-6852-336f-7321-5b4df69fd430@arm.com>
Date: Thu, 9 Mar 2023 13:13:11 +0000
From: Robin Murphy <robin.murphy@....com>
To: Nicolin Chen <nicolinc@...dia.com>, jgg@...dia.com, will@...nel.org
Cc: eric.auger@...hat.com, kevin.tian@...el.com,
baolu.lu@...ux.intel.com, joro@...tes.org,
shameerali.kolothum.thodi@...wei.com, jean-philippe@...aro.org,
linux-arm-kernel@...ts.infradead.org, iommu@...ts.linux.dev,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 06/14] iommu/arm-smmu-v3: Unset corresponding STE
fields when s2_cfg is NULL
On 2023-03-09 10:53, Nicolin Chen wrote:
> From: Eric Auger <eric.auger@...hat.com>
>
> Despite the spec does not seem to mention this, on some implementations,
> when the STE configuration switches from an S1+S2 cfg to an S1 only one,
> a C_BAD_STE error would happen if dst[3] (S2TTB) is not reset.
Can you provide more details, since it's not clear whether this is a
hardware erratum workaround or a bodge around the driver itself doing
something wrong like not doing a proper break-before-make transition of
the STE. The architecture explicitly states that all the STE.S2* fields
except S2VMID and potentially S2S are ignored when Stage 2 is bypassed.
Thanks,
Robin.
> Explicitly reset those two higher 64b fields, to prevent that.
>
> Note that this is not a bug at this moment, since a 2-stage translation
> setup is not yet enabled, until the following patches add its support.
>
> Reported-by: Shameer Kolothum <shameerali.kolothum.thodi@...wei.com>
> Signed-off-by: Eric Auger <eric.auger@...hat.com>
> Signed-off-by: Nicolin Chen <nicolinc@...dia.com>
> ---
> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> index c5616145e2a3..29e36448d23b 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> @@ -1361,6 +1361,9 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
> dst[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK);
>
> val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS);
> + } else {
> + dst[2] = 0;
> + dst[3] = 0;
> }
>
> if (master->ats_enabled)
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