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Message-ID: <CAJM55Z9YGjD+1haWcXEZNkHnWNRZckdBmTTykTt7QZV_LUohgQ@mail.gmail.com>
Date:   Thu, 9 Mar 2023 15:06:13 +0100
From:   Emil Renner Berthing <emil.renner.berthing@...onical.com>
To:     Hal Feng <hal.feng@...rfivetech.com>
Cc:     linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        linux-riscv@...ts.infradead.org, Stephen Boyd <sboyd@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor@...nel.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Ben Dooks <ben.dooks@...ive.com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on
 clock driver

 On Thu, 9 Mar 2023 at 10:44, Hal Feng <hal.feng@...rfivetech.com> wrote:
> On Tue, 28 Feb 2023 10:42:35 +0800, Hal Feng wrote:
> > On Sun, 26 Feb 2023 18:34:52 +0100, Emil Renner Berthing wrote:
> >> On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@...rfivetech.com> wrote:
> >>> From: Emil Renner Berthing <kernel@...il.dk>
> >>>
> >>> Add driver for the StarFive JH7110 always-on clock controller
> >>> and register an auxiliary device for always-on reset controller
> >>> which is named as "reset-aon".
> >>>
> >>> Reported-by: kernel test robot <lkp@...el.com>
> >>> Signed-off-by: Emil Renner Berthing <kernel@...il.dk>
> >>> Co-developed-by: Hal Feng <hal.feng@...rfivetech.com>
> >>> Signed-off-by: Hal Feng <hal.feng@...rfivetech.com>
> >>> ---
> >>>  drivers/clk/starfive/Kconfig                  |  11 ++
> >>>  drivers/clk/starfive/Makefile                 |   1 +
> >>>  .../clk/starfive/clk-starfive-jh7110-aon.c    | 156 ++++++++++++++++++
> >>>  3 files changed, 168 insertions(+)
> >>>  create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c
> >>>
> >>> diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
> >>> index 4640d0665d1c..2aa664f2cdee 100644
> >>> --- a/drivers/clk/starfive/Kconfig
> >>> +++ b/drivers/clk/starfive/Kconfig
> >>> @@ -31,3 +31,14 @@ config CLK_STARFIVE_JH7110_SYS
> >>>         help
> >>>           Say yes here to support the system clock controller on the
> >>>           StarFive JH7110 SoC.
> >>> +
> >>> +config CLK_STARFIVE_JH7110_AON
> >>> +       tristate "StarFive JH7110 always-on clock support"
> >>> +       depends on CLK_STARFIVE_JH7110_SYS
> >>> +       select AUXILIARY_BUS
> >>> +       select CLK_STARFIVE_JH71X0
> >>> +       select RESET_STARFIVE_JH7110
> >>> +       default CLK_STARFIVE_JH7110_SYS
> >>
> >> As far as I can tell the JH7110 boots fine without this driver and it
> >> already depends on the _SYS driver above, so please do
> >>
> >> default m if SOC_STARFIVE
> >
> > OK. Will fix it.
>
> Hi, Emil,
>
> The AON clock driver provides clocks for gmac0 which is used frequently.
> So I think it would be more convenient if we set "default y" here.

You're right that if we default y for the ethernet driver then the aon
clock/reset should also default y. Personally I don't think we should
default y for every ethernet driver that might be used on some
supported risc-v platform, but I see now that
arch/riscv/config/defconfig already contains CONFIG_MACB=y,
CONFIG_E1000E=y, CONFIG_R8169=y and CONFIG_MICROSEMI_PHY=y, so maybe
I'm wrong or just too late.

> Best regards,
> Hal

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